Welcome
| Highlights |
| Applications |
V1730 digitizer is provided with FPGAs that can run Digital Pulse Processing firmware for Physics Applications:
|
| GENERAL |
Form Factor 1-unit wide, 6U VME64 |
ANALOG INPUT |
Channels 16/8 channels single ended Impedance 50 Ohm Connector MCX Full Scale Range 0.5 or 2 Vpp SW selectable Bandwidth
250 MHz Offset Programmable DAC for DC offset adj. Range: ± 1 V |
DIGITAL CONVERSION |
Resolution 14 bits Sampling Rate
500 MS/s Simultaneously on each channel |
| ADC CLOCK GENERATION |
Clock source: internal/external On-board PLL provides ADC sampling clock generation from an internal (50 MHz loc. oscillator) or external (front panel CLK-IN connector) reference |
DIGITAL I/O |
CLK-IN (AMP Modu II) AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by custom cable) Jitter<100ppm TRG-IN (LEMO) External trigger input NIM/TTL, Zin = 50 Ohm CLK-OUT (AMP Modu II) DC coupled differential LVDS clock output locked at ADC sampling clock (Freq.: 500 MHz) TRG-OUT (LEMO) Local trigger output NIM/TTL, Rt = 50 Ohm S-IN (LEMO)
SYNC/START front panel input NIM/TTL, Zin = 50 Ohm |
| MEMORY |
640 kS/ch or 5.12 MS/ch Multi-Event Buffer with independent read and write access divisible into 1 ÷ 1024 buffers Programmable event size and pre-post trigger |
TRIGGER |
Trigger Source Trigger Propagation TRG-OUT digital output Trigger Time Stamp Standard FW, DPP-ZLE FW: 31-bit counter, 16 ns resolution, 17 s range DPP-PSD FW: 31-bit counter, 2 ns resolution, (4 s range), expandable to 64-bit DPP-PHA FW: 30-bit counter, 2 ns resolution (2 s range), expandable to 64-bit |
SYNCHRONIZATION |
Clock Propagation Daisy chain (VME only) through CLK-IN/CLK-OUT connectors One-to-many clock distribution from an external clock source Clock Cable delay compensation Acquisition Synchronization
Sync Start/Stop through digital I/O (S-IN or TRG-IN input, TRG-OUT output) External Trigger Time Stamp reset |
| ADC & MEMORY CONTROLLER FPGA | Altera Cyclone EP4CE30 (one FPGA serves 4 channels) |
| ANALOG MONITOR |
12-bit/100 MHz DAC FPGA controlled output with four operating modes: Trigger Majority / Test Pulses / Memory Occupancy / Voltage Level |
| LVDS I/O |
16 general purpose LVDS I/Os controlled by FPGA Busy, Data Ready, Memory Full, Individual Trg-Out and other functions can be programmed An Input Pattern from the LVDS I/Os can be associated to each trigger as an event marker |
COMMUNICATION INTERFACE |
Optical Link CAEN CONET proprietary protocol, up to 80 MB/s transfer rate Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod.A2818/A3818) VME
VME 64X compliant Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s) |
| FIRMWARE |
Standard Firmware Digital Oscilloscope function Factory provided with the digitizer Upgrades Firmware can be upgraded via Optical Link or VMEbus DPP Firmware
Special firmware for Digital Pulse Processing DPP-PSD, DPP-PHA supported DPP-ZLEplus COMING SOON |
| POWER CONSUMPTIONS |
V1730 8.2 A @ +5V 840 mA @ +12V -12 V not used V1730C T.B.D. V1730B
10.2 A @ +5V 840 mA @ +12V -12 V not used V1730D T.B.D. |
| Description | Release | Date | OS-Version | Environment | Download |
|---|---|---|---|---|---|
| Firmware CONET2 Compliant | |||||
x730 DPP-PHA FW (C) |
4.11_139.6 | March, 2017 | |||
| FW Package 1.58 MB - Type: .cfa |
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| Release Notes 5.71 KB - Type: .txt |
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|
x730 DPP-PSD FW (B) |
4.11_136.11 | March, 2017 | |||
| Release Notes 8.38 KB - Type: .txt |
|
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| FW Package 1.54 MB - Type: .cfa |
|
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|
x730 Waveform Recording FW |
4.16_0.7 | September, 2017 | |||
| FW Package 1.25 MB - Type: .cfa |
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| Release Note 4.93 KB - Type: .txt |
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| Related Models | ||
| Family | Name | Description |
|---|---|---|
| Digitizer Software | CAENScope | Digitizer Software for Signal Inspection and Waveform Recording (New Version) |
| Digitizer Software | CAEN WaveDump | CAEN Digitizer readout application |
| Digitizer Software | CAENDigitizer Library | Library of functions for CAEN Digitizers high level management |
| Digitizer Software | CAENUpgrader | Firmware Upgrade Tool for Front-end Boards Bridges & VME Power Supply |
| Digitizer Firmware | DPP-PSD | Digital Pulse Processing for the Pulse Shape Discrimination |
| Digitizer Software | MC˛Analyzer | Digital MCA Data Acquisition and Analysis Software |
| Code | Description |
|---|---|
| WV1730BXAAAA | V1730B - 16 Ch. 14 bit 500 MS/s Digitizer: 5.12MS/ch, CE30, SE |
| WV1730XAAAAA | V1730 - 16 Ch. 14 bit 500 MS/s Digitizer: 640kS/ch, CE30, SE |
| WV1730CXAAAA | V1730C - 8 Ch. 14 bit 500 MS/s Digitizer: 640kS/ch, CE30, SE |
| WV1730DXAAAA | V1730D - 8 Ch. 14 bit 500 MS/s Digitizer: 5.12MS/ch, CE30, SE |
| Manuals | Last Update |
|---|---|
| UM2792 - V1730/VX1730 & V1725/VX1725 User Manual | June 10th, 2016 |
| UM2580 - DPP-PSD User Manual | 29 September, 2016 |
| UM5118 - 725-730 Waveform Recording Firmware Registers | December 6th, 2016 |
| UM3182 - DPP-PHA and MC2Analyzer User Manual | June 20th, 2017 |
Precautions for Handling Storage and Installation
| Slide Presentations | Last Update |
|---|---|
| SP5148 - Digital systems for Multi-Parametric analysis in Physics Applications (India - March 2016) | March, 2016 |
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