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CAEN Digitizer Whitepaper

As a result of its multi-year experience in electronic design for Nuclear Physics, CAEN offers a wide selection of digitizers to cover the most typical applications in Radiation Detection, from Research to Industry, like Nuclear Particle and Astroparticle Physics, Fusion Plasma Diagnostics, Homeland Security, Environmental Monitoring, and Medical Imaging.
The Digitizer represents the new digital revolution in setups from the lab to the large experiment, being able to replace multiple traditional modules (Multi Channel Analyzers, QDCs, TDCs, Discriminators, and others) with a single board.
The digitizer families provided by CAEN differ in sampling frequency, ADC resolution, number of analog channels, form factor, digital memory size, and other features as to overcome the limits of the detector’s classic analog acquisition chain.

Analog VS Digital

From multiple boards, cables and manual adjustment …

  • No flexibility: functions hard-coded in electronic circuits!

 

… to a single multi-purpose board controlled by a software

  • Flexibility, small size and weight, stability, scalability, good performances

Digitizer principle of operation

Introduction

Basically, the Digitizer is an electronic device that continuously acquires analog pulses, passing through an analog input stage of signal conditioning, an analog-to-digital conversion by fast ADCs, and storage of the digitized samples as event data into digital memories, where they can be read out by a host computer through fast commmunication interfaces (USB, VMEbus, Optical Link, Ethernet).

Digitizers based on FLASH ADCs acquire digitized events consecutively using multi-buffer memory management, so that writing and reading take place with a significantly reduced dead-time (typically, few tens of nanoseconds). Each channel is able to digitally discriminate the input pulse online and generate a trigger when a pre-determined condition is met. Digitizers based on Switched Capacitor Array ADCs are charachterized by a high sampling frequency and channel density. They store events in analogic memory buffers, then digitize and save them when an external trigger arrives, resulting in an AD conversion dead-time (from tens to around two hundreds microseconds).

All CAEN digitizers are equipped with on-board CPU, based on Field Programmable Gate Arrays (FPGA), giving the capability to process in real-time the information coming fron the ADCs, making so possible to perform several operations at the same time:

  • Waveform recording
  • TDC (Time to Digital Converter)
  • QDC (Charge to Digital Converter
  • PHA (Pulse Height Analysis)
  • PSD (Pulse Shape Discriminator)
  • ZLE (Zero Suppression based on the Zero Length Encoding)
  • DAW (Data reduction based on the Dynamic Acquisition Window)
  • Logic operations (Coincidence logic/Majority/Veto/Gate)

Waveform inspector and recording

By default, the Digitizer is equipped with a raw waveform firmware that makes it work just as a waveform recorder, similarly to a digital oscilloscope. Outgoing stream of digital samples from the ADC is continuously read by the FPGA and stored in the digital memory, that is a multi-event circular buffer of a programmable size. At the arrival of the trigger, the buffer is frozen and made available for the readout, while the acquisition can continue into a new buffer. No digital pulse processing is applied in the FPGA, but the digitized raw waveforms can be further elaborated offline by the User.

Waveform recording firmware features:

  • “Slow” input signals with good energy resolution coming from detectors coupled with Charge Sensitive Preamplifiers (like HPGe, Silicon, etc.), typically requiring ADC frequency from 50 to 200 MS/s
  • Input Signals with high time resolution from fast detectors coupled with PMT, SiPM, etc., typically requiring ADC from 250 MS/s to 1 GS/s and higher (like 5 GS/s with Switched Capacitor Arrays)
  • Event acquisition based on a global trigger (software, external or channel-trigger)

Programmable acquisition window and post-trigger

Digital Pulse Processing

How it works in our digitizers

The DPP (Digital Pulse Processing) firmware is a special firmware which implements an algorithm running in real time in the FPGA. With a simple firmware upgrade, the Digitizer is then capable of various physics measurements, The acquisition takes place upon the channel self-trigger and independently for each channel. In this way, only the events from the firing channels are taken. Accordig to the DPP algorithm, the FPGA processes each digitizer wave and extracts physical quantities like time (timestamp), energy, PSD, etc.

Data is grouped into compact formats (List mode), thus allowing the board to have high throughput. Despite the DPP firmware is optimized for the readout of the physical quantities, portions of waveform can be also retrieved for further post-processing (typically a short piece around the trigger time arrival).

The DPP firmware is a pay firmware that is free downloadable from CAEN website. If no license is loaded on the digitizer, the firmware runs in Trial mode for evaulation: fully functional for 30 minutes per power-cycle. Time limitation is removed by purchasing a license and storing it on the digitizer.

Immagine esplicativa
Immagine esplicativa

DPP - timing and correlations

Digital CFD (Constant Fraction Discrimination) and LED (Leading Edge Discrimination) implemented onboard for a fine time stamp resolution.

  • Fine time stamp steps of 1 ps for 751 family, 2 ps for 730, and 4 ps for 725 family
  • Time correlation among channels for Time of Flight (ToF)/ Start-Stop measurements, etc.
  • ToF resolution for 22Na with BaF2 detectors: 182 ps
  • ToF resolution for 60Co with BC501A detectors: 230 ps

See for example AN6872, AN3251, AN5157
Check your board here

DPP – Gated QDC and Pulse Shape Discrimination

Typical input pulses from detectors with PMTs, without the use of preamplifiers, or at least with mid-fast preamplifiers.

The input pulse is analyzed by the FPGA, in particular:

  • Baseline subtracted
  • Gate for charge integration
  • Double Gate for pulse shape discrimination

Typical energy resolutions:

  • 3.0 % @ 137Cs for LaBr3
  • 5-8 % @ 137Cs for NaI(Tl)

Typical PSD resolutions for neutron/gamma (FoM = centroid_difference/ (FPHM_gamma + FWHM_Neutron) ):

  • FOM > 2.0 for E > 300 keV, FOM > 2.5 for E > 580 keV

See for example AN6872, AN3250
Check your board here

DPP - Pulse Height Analysis

Digital MCA, accepting signals from HPGe, Silicon, multi wire chambers, coupled with charge sensitive/transistor reset preamplifier, without the use of a Shaping Amplifier. It can work with PMTs or faster preamplifiers too.

Typical features of a PHA system:

  • Trapezoid shaping (replacing the gaussian shaper)
  • Trap. Baseline subtraction to evaluate the trap. height
  • Ballistic effects correction
  • Add back for clover detectors

Typical energy resolutions:

  • 1.8 keV @ 60Co for HPGe
  • From 1.5 to 2.5 keV @ [120-1460] keV for Clover add-back

See for example AN6896, AN5830, AN5157, AN3110
Check your board here

DPP – Zero Suppression and Dynamic Acquisition Window

Zero Length Encoding

  • Long waveform acquisition
  • Suppression of zeros (baseline)
  • Acquisition of relevant information only
  • Common trigger

 

Dynamic Acquisition Window

  • Waveform acquisition
  • Automatically adjustment of the acquisition window with the pulse duration
  • Channel-independent trigger

Software

CoMPASS

  • CoMPASS can manage the acquisition of multiple boards with non-homogeneous DPP firmware
  • Easy manipulation of data:
    • Multiple Spectra with ROI and statistics
    • Runtime data correlation (energy and time filters/add back/PSD cuts, etc.)
    • Data socket for user runtime analysis
    • Compliant with ROOT
    • Several output format

Switched Capacitors

x742 and x743 Digitizer Family

742 – DRS4 chip (designed @PSI ) &
743 – SAMLOG chip (designed @CEA/IRFU & CNRS/IN2P3/LAL)

  • High frequency analog sampling (up to 5 GS/s)
  • High density channels
  • 1024 cells storage (capacitors)
  • Sampling/holding functioning
  • Drawback: high dead-time (180 us/125 us)

Similar Performances in time measurement but…

  • 742 digitizers can measure
    • Relative time between two signals fed in the same chip
    • Relative time between one channel signal and the trigger signal
  • 743 digitizers have sychronous sampling so the reference is the same
    Sampling and Trigger are advantages of 743 family
    Memory buffer is an advantage of the 742 family

Open FPGA Digitizer

x560 Digitizer Family

Maximum flexibility for several applications

  • R5560/R5560SE
    • 128-channels (diff. or single-ended) rackmount for large experimental installation
    • Readout of large arrays of detectors, especially in neutron detection applications
  • DT5560SE
    • 32-Channels Desktop form factor for lab development and testing
    • Maximum readout flexibility: USB3.0, Ethernet and Optical Link
  • Fully supported by SCI-Compiler for easy-FPGA programming

The next generation of Digitizers

Digitizer 2.0

Improvement of Performances, Open FPGA and embedded ARM

  • More density, faster sampling rate, higher resolution for higher performances
  • Increased communication readout through 1/10 Gb Ethernet, USB 3.0 (yet keeping proprietary CONET)
  • Easier multi-board synchronization (clock and timing distribution)
  • Increase of acquisition memory buffer size: from SSRAM to DDR4 (=> from MBs to GBs)
  • Single FPGA (Xilinx Zynq US+ ) architecture => more resources for DPP algorithms and support for “Open FPGA
  • Embedded quad-core ARM (Linux) => middleware, web interface. Possibility to run user Data Processing SW

 

Model # Channels MS/s # bit Applications
x2740 64 125 16 64 MCAs for high channel density spectroscopy
Good fit for Neutrino and Dark Matter exp. (candidate for Dark Side)
x2751 (*) 16 1000 14 Ultra-fast detectors with ps timing applications
x2725/x2730 (*) 16 250/500 14 Medium-fast detectors
Sub-ns timing combined with high energy resolution
x2724 (*) 32 125 16 Spectroscopy & MCA
Advanced Front-End (gain, shaping, …)
Semiconductor detector (HPGe, Clover, SDD, …)
Typically connected to charge Sensitive Preamplifier

(*) Coming soon. Product specifications are subject to change without notice.

Summary

Digitizer Summary

Model Form factor # Channels MS/s # bit Wave Recording Zero Suppression Dinamic Acquisition Window PHA PSD CFD QDC Open FPGA
x720 VME/NIM/Destkop 8/4/2 250 12
x724 VME/NIM/Destkop 8/4/2 100 14
x725 VME/NIM/Destkop 16/8 250 14
x730 VME/NIM/Destkop 16/8 500 14
x740 VME/NIM/Destkop 64/32 62.5 12
x751 VME/NIM/Destkop 8/4/2 1000 – 2000 10
x761 VME/NIM/Destkop 2/1 4000 10
x742 VME/NIM/Destkop 32+2 / 16+1 5000 12
x743 VME/NIM/Destkop 16/8 3200 12
x5560 Rack/Destkop 32/128 250 14
x27xx VME/Destkop 16/64 125 – 1000 14/16

Acquisition Modes Summary

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