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Sci-Compiler SMART

New

Evaluation and learning kit for SCI-Compiler

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Features

  • Beginners’ kit to learn how to easily program an open FPGA
  • Powered by SCI-Compiler, the block-diagram-based firmware generator and compiler for CAEN programmable boards
  • Automatic VHDL code generation starting from logic blocks and virtual instruments
  • Very simple generation of complex online pulse processing: schematics-based design
  • Hardware included for custom pulse processing firmware testing
  • Ideal for non-expert firmware programmer
  • Advanced signal processing blocks like PHA based on Trapezoidal Filter, Charge Integration, Oscilloscope …
  • Automatic generation of drivers, libraries and demo software
  • 2 channel, 65MS/s 12 bit, Open FPGA ADC unit included
More info
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Overview

Sci-Compiler SMART (SCISMART) is a hardware + software kit for non-expert users who are approaching the open FPGA programming.
We introduce them to an innovative method to simplify the firmware development using Sci-Compiler software, a block-diagram-based programming interface consisting of a prebuilt set of functions (for example oscilloscope, TDC, MCA, charge integration, etc.) specifically developed for physics/engineering applications. Placing and interconnecting the available blocks on a diagram, SCI-Compiler is able to automatically generate a VHDL piece of code that implements the required function and deploy it to the FPGA. In this way, even a non-expert user can write his own firmware code without having any knowledge of the VHDL/Verilog programming language.
SCI-Compiler SMART is composed of a SCI-Compiler license and a basic hardware (DT1260 unit), designed for the exact purpose of evaluating the software and learning how to design custom firmware using the block diagram method. It includes:

  • 1x DT1260, 2 Channel, 65 MS/s, 12 bit ADC unit with Open FPGA
  • 1x SCI-Compiler Lite license working with the DT1260 unit only

The kit allows to develop both FPGA firmware for custom digital pulse processing and software application for data readout, using the generated libraries. It is therefore possible to access registers of the DT1260 and transfer data to the PC in list, waveform or user-customizable format.
A basic, ready-to-use default firmware and readout software is provided for free and open source. The default firmware manages the basic waveform digitization and Pulse Height Analysis. The user can take advantages of examples firmware diagram available in SCI-Compiler, in order to start learning how to program the FPGA and take confidence with the software.

A complete set of tools!
SCI-Compiler comes with 100+ virtual blocks that works exactly as real laboratory instrumentation.

I/O INTERFACE

iointerface
Control Digital and Analog Input/Output of the hardware devices.

LOGIC GATE

logicgate
A rich library that contains coincidence logic, boolean functions, Gate and Delay, counters, timers, scaler, frequency meters, array of bit manipulation.

OSCILLOSCOPE

oscilloscope
Probe signals of each acquiring channel, even in the middle of the processing chain.


IMAGING

hightlights
Online image processing capabilities for medical applications, astronomy and high energy physics.

TRAPEZOIDAL FILTER

trapezoidal filter
Trapezoidal filter allows to achieve the optimum resolution on HpGE and PMT detectors.

ONLINE SPECTRUM

online spectrum
Energy/Time Spectrum can be calculated onboard. Online spectrum allows readout thousands of channels per second.


TDC AND TIMESTAMPING

hightlights
Timestamp events with 2 ns resolution and calculate TOT. Digital CFD increase 10x the timing resolution on analog signals.

PSD

trapezoidal filter
Pulse Shape Discrimination algorithm to allows for particle identification.

ANALOG SHAPER

online spectrum
High pass and Low pass real-time filter can be combined to emulate a traditional analog shaping chain.

 

OS Windows Framework required Supported CAEN Board Local Compiler option (*) Remote Customization Service

Windows 10 – 64 bit

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4.0 or higher

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 SMART kit 2020.2 blank AVAILABLE

Technical Specifications

GENERAL

Form Factor 72x22x84 mm3 (WxHxD) Desktop

POWER CONSUMPTION

0.3 A @ 5 V (Typ.), power over USB

ANALOG INPUT
Channels

2 single-ended input

Connector

2x LEMO

Bandwidth (-3 dB)

Max. dynamic range: 25 MHz

Small amplitude (200 mV): 30 MHz

Input impedance

1 kΩ / 50 Ω jumper selectable

 Noise Level

1 LSB rms, 3 LSB p-p

Full Scale Range

4 Vpp

Offset

Programmable [0:4096] LSB

Non-linearity < 0.15%

Minimum offset 0 corresponds to values in the range [50:100] LSB
DIGITAL I/Os
Channels

2 general purpose programmable digital I/Os

Single-ended

Connector

2x LEMO

 Signal Type

TTL

Input impedance

1 kΩ / 50 Ω jumper selectable

Maximum rate

25MHz IN, 32 MHz out
DIGITAL CONVERSION

Resolution: 12 bits

Non Linearity: < 0.15%

Sampling Rate: 65 MS/s Simultaneously on each channel

MEMORY
FPGA onchip memory

200 Kbytes of fast FPGA memory.
Memory can be arbitrary partitioned for
specific task using Sci-Compiler

 FPGA onchip memory user available

> 95% of total onchip memory

Example: 2 channel, 12 bit resolution waveform digitizer → 32 ksamples per channel memory depth use about the 65 % of available memory

TRIGGER
Trigger Source

– Internal (default firmware): managed by the default firmware, using a fast trapezoidal filter.

– External: from LEMO, edge sensitive Software triggered acquisition.

– Complex trigger logic: implementable by the user on the open FPGA.

 Trigger timestamp

– 32 bit counter, 16.6 ns resolution with default trigger

– Possibility to increase the resolution using the Digital Costant Fraction Discrimination algorithm present in Sci-Compiler.

– Resolution depends on input signal characteristics
FPGA

Open FPGA

Xilinx Spartan7-LX25

SYNCRONIZATION

Custom SYNC

User multi-board synchronization can be achieved with custom Sci-Compiler firmware using the two LEMO connectors as clock/t0/trigger source

COMMUNICATION INTERFACE
USB 2.0

Micro-USB

Firmware upgrade

Via USB using Open Hardware stand alone software or directly from SCI-Compiler

JTAG

Jtag connector available for firmware debugging using Vivado

Logic Analyser (to access to JTAG connector the box must be removed)

 LED

2 user programmable green LED + 1 blu led power/bootloader indicator

GPIO (for OEM integration)

– 8 GPIO, 3.3V directly connected to FPGA PIN. (to access to GPIO connector the box must be removed)

– GPIO can be used to implement also serial (UART/I2C) interfaces using Sci-Compiler/Vivado
FIRMWARE
Default

– Waveform recording Pulse Height Analysis with trapezoidal filter

– Default firmware distributed open source as SCI-Compiler projects

 Custom

– Use SCI-Compiler to develop your own firmware!
LICENSE INCLUDED

– Serveral firmware examples included in SCI-Compiler
FIRMWARE UPGRADE

Firmware can be upgraded via micro USB

SOFTWARE

– SCI-55X0 Readout Software to manage the default firmware

– SCI-Compiler for custom firmware development

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WKSCISMARTXA SCI-Compiler SMART kit   RoHS

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