FERS-5200 Boards

A5202 - DT5202

The A5202 (DT5202) is the boxed version for desktop use) is the FERS-5200 unit that uses the Citiroc‐1A chip produced by WeeROC for SiPM readout. More precisely, the A5202 is a small board (∼7 ×17 cm²) housing two Citiroc‐1A chips (64 readout channels). Each readout channel is composed of a Preamplifier, a Slow Shaper with peak sensing detector and a Fast Shaper followed by a discriminator. Peak sensing values from each Citiroc‐1A are converted sequentially (multiplexed output) by an ADC. The 64 channel self‐triggers (discriminator outputs) can be used for counting, time stamping, to determine the Time over Threshold (ToT) information and also to generate the board bunch trigger that starts the A/D conversion. The A5202 board is also provided with the A7585D power supply module for biasing the SiPMs.

A5203 - DT5203

The A5203 (DT5203) is the boxed version for desktop use) is the FERS-5200 unit that uses the picoTDC chip produced by CERN for high-resolution time measurements. More precisely, the A5203 is a small board (∼7 ×17 cm²)  operating as a 64 channels TDC with 3,125 ps LSB resolution. Each readout channel can accept LVDS signals and measure their rising/falling edge timestamps. In this way, the unit is able to reconstruct Time of Arrival of signals as an absolute timestamp or as a ΔT with respect to a common Tref pulse, as well as the Time over Threshold that allows for amplitude estimation or walk correction.

The ToT allows for amplitude estimation, energy spectrum reconstruction, and timing walk correction, and it also enables the possibility to achieve optimal timing resolution with no need of Constant Fraction Discriminators. For small setups a single A5203 unit can be used stand alone, without any additional hardware, by simply connecting the unit to a PC via USB 2.0 or Ethernet 10/100T. For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink.

A5204 - DT5204

The A5204 (DT5204 is the boxed version for desktop use) is the FERS-5200 unit that houses the WeeROC Radioroc 2 and CERN picoTDC chips for SiPM readout with high-resolution time in just ∼7 ×20 cm². Besides a slow shaper with a pulse height detector for the data acquisition, the Radioroc 2 ASIC includes configurable fast pre-amplifiers followed by fast shapers and discriminators that can output 64 individual channel triggers with jitter as low as 55 ps FWHM on a single p.e. The individual channel triggers are connected to the FPGA, for photo-counting up to 200 MHz as well as for the implementation of coincidences, majority and topological acquisition triggers. The individual triggers are also connected to the picoTDCchip, thet allows for very precise timing measurements thanks to the 3.125 ps LSB. Time Over Threshold (ToT) can also be used to estimate the pulse height, making it possible to acquire time stamp and PHA with very low dead time and extremely high rate, without the need of the multiplexed A/D conversion.

 The A5204/DT5204 board is also provided with the A7585D power supply module for biasing the SiPMs.

DT5215

One DT5215 (FERS Concentrator Board) can manage up to 8 TDlinks. Each TDlink can connect and manage up to 16 FERS units in daisy chain, for a total of 128 units. For 64-channels cards, this means 8192 channels read out by a single Concentrator. Multiple concentrator boards can be synchronized to further extend the total number of channels. The Data Concentrator is connected to the Host computer through 1/10 Gb Ethernet or USB 3.0.

The Concentrator Board manages the data readout from the network of FERS units and the event data building according to the time stamp and/or trigger ID of the event fragments acquired by each unit. Sorted and merged data packets are then stored to the local memory and finally sent to the host computers. Custom algorithms for data processing and reduction can be uploaded by the user onto the embedded CPU ^{(COMING SOON)}.

 

One computer, one Concentrator, thousands of channels

FERS-5200 is an extendable system: the same FERS unit can be used as stand-alone system for prototyping and validation, and then added to a greater network tree for the readout of large arrays. This strategy eliminates waste and maximizes cost efficiency.

The core of the scalability of the FERS-5200 is the optical TDlink, which manages simultaneously data stream, unit synchronization and slow control.

The concentrator board DT5215 hosts 8 optical links, each capable of sustaining up to 16 FERS units in daisy chain. In the case of A5202/A5203, this means 8192 channels managed by a single Concentrator board… and multiple Concentrator board can be synchronized to support a limitless number of channels!

 

Janus software

Janus is open-source software for controlling and reading FERS-5200 boards. It comes in two versions, Ver. 5202 and Ver. 5203, and serves as a platform for custom DAQ development tailored to specific needs. Users can customize data processing, acquired statistics, and output file formats.

Janus can handle up to 16 connected FERS units via Ethernet or USB, including readout of the DT5215 Concentrator Board, offering a unified user interface. Janus is composed of two parts: one in C, the core application, and one in Python for the user interface. Plots are generated using Gnuplot, and all configuration parameters are stored in a text-based config file.

You can use Janus in two modes:

• Console Mode: Edit the configuration file, launch a text console, and receive messages and statistics during the run. Plotting is done through Gnuplot.
• GUI Mode: Run the Python program to connect to the C program via a socket. Send commands and receive messages displayed in the Python GUI.