- Two simultaneous ranges: 120 and 900 pC
- 25 fC LSB
- 12-bit resolution (15 bit total dynamic range)
- 0.8 ms / 16 ch conversion time
- Integral non linearity: ±6.5 counts (low range); ±2.5 counts (high range)
- Gate width: from 100 ns to 5 µs
- Noise: ±1 count
- 2% interchannel uniformity
- 300 ns recovery after Fast Clear
- Positive, negative or differential input signals
The Mod. C205 A is a double width CAMAC unit housing 16 charge integrating ADC channels. For each channel, the input charge, received when the GATE signal is active, is converted to a voltage level through a Charge to Voltage Converter (CVC); each CVC output voltage is then amplified by both a 1X-gain amplifier and a 7.5X-gain amplifier, and sequentially transformed into two corresponding 12-bit words through two parallel 12-bit Analog to Digital Converters (ADC): this allows to achieve a 15 bit total dynamic range. Meanwhile, a BUSY output signal is available at the corresponding pins of the 10-pin front panel connector. Each couple of words corresponding to a conversion value is stored into a RAM-type internal memory (readable via CAMAC) in sequential order.
At the end of the analog-to-digital conversion of the last input signal, a LAM signal is generated. At this point the conversion values corresponding to each input charge can be read via CAMAC.
The TEST input connector allows the user to perform test operation by using a single input signal common for all channels.
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Technical Specifications
|
Packaging |
2-unit wide |
|
Inputs |
DC coupled, 50 Ohm impedance for positive or negative input signals; 110 Ohm for differential input signals |
|
Input offset voltage |
± 2 mV |
|
Full scale |
120 pC (15 bit), 900 pC (12 bit) |
|
Conversion time |
0.8 ms/16 ch |
|
Conversion gain |
31 counts/pC (15 bit), 4 counts/pC (12 bit) |
|
Gain dispersion |
± 2 counts max |
|
Integral non linearity |
within ± 6.5 counts (15 bit), ± 1.6 counts (12 bit) |
|
GATE width |
100 ns to 5 µs |
|
GATE timing |
The GATE signal must precede the analog input by > 65 ns |
|
TEST input sensitivity |
about 30 times less than a channel |
|
Pedestal/GATE width coefficient |
50 counts/100 ns (15 bits), 7 counts/100 ns (12 bits) typical total pedestal: 350 counts (15 bits), 50 counts (12 bits) typical |
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