I/O Registers

Digital

Photo of I/O Registers

The I/O Registers family provides flexible digital interfacing, signal routing, and programmable logic capabilities for test benches and complex data acquisition systems. These modules can operate as general-purpose input/output registers, pattern units, or fully programmable FPGA-based logic controllers, enabling the implementation of custom trigger logic, coincidence matrices, gate and delay generation, and signal monitoring within a single hardware platform.

Designed for high-speed laboratory environments, the family supports multiple logic standards (NIM, TTL, ECL, LVDS) and allows individual channel masking, software-controlled signal generation, and real-time status monitoring. Advanced FPGA-based units extend functionality with user-programmable firmware, high channel density, and expandable I/O interfaces, making them suitable for building complex digital control and synchronization architectures in modern experiments.

  • General-purpose I/O registers and FPGA-based programmable logic units for trigger, timing, and control

  • Support for multiple logic standards with per-channel configuration, masking, and monitoring

  • High channel density with expandable I/O interfaces and user-programmable firmware

  • Real-time control via VME, USB, or Ethernet with interrupt, gate, and delay management

I/O Registers Models

Grid Compare
DT5495

DT5495

  • User Programmable FPGA

  • Compact Desktop form factor

  • Up to 162 inputs, up to 130 outputs
V977

V977

  • NIM and TTL inputs/outputs

  • Individual channel enabling/disabling

  • Software Input/Output generation
V2495

V2495

  • User customisable FPGA Unit

  • LVDS/ECL/PECL inputs (differential)

  • 64 inputs, expandable to 162 (with 32 outputs)
Image
Name
Package
No. of Sections
Function
Inputs per Section
Outputs per Section
In Connectors
Out Connectors
DT5495

DT5495

Desktop

1

Programmable I/O register FPGA: Cyclone V 5CGXC4 (50 K LEs)

64 ECL/PECL/LVDS +2 bidirectional NIM/TTL (expandable up to 162)

32 LVDS +2 bidirectional NIM/TTL (expandable up to 130)

Robinson Nugent Flat/LEMO

Robinson Nugent Flat/LEMO
V977

V977

VME

1

Pattern Unit, I/O register

16 NIM / TTL

16 NIM / TTL

LEMO

LEMO
V2495

V2495

VME

1

Programmable I/O register FPGA: Cyclone V 5CGXC4 (50 K LEs)

64 ECL/PECL/LVDS +2 bidirectional NIM/TTL (expandable up to 162)

32 LVDS +2 bidirectional NIM/TTL (expandable up to 130)

Robinson Nugent Flat/LEMO

Robinson Nugent Flat/LEMO