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1 analog input, 14-bit @ 200 MS/s, 50 Ω
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Scope & DPP modes with internal memory buffer
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Open FPGA – user firmware via Sci-Compiler
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USB 2.0 and 10/100 Mb Ethernet interfaces
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Compatible with WaveDump and CoMPASS
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Available as desktop version
The DT5571 is a high-performance waveform digitizer featuring 14-bit resolution and a 200 MS/s sampling rate on a single analog input. Designed to meet the needs of modern acquisition setups, it combines precision, speed, and flexibility in a streamlined desktop form factor.
Two operating modes are supported: Scope Mode for raw waveform recording, and DPP Mode for real-time on-board signal processing. With software-selectable input polarity and an internal memory buffer, the DT5571 is ideal for reading out scintillators, SiPMs, and other fast detectors.
The module offers USB 2.0 and 10/100 Mb Ethernet interfaces for fast data transfer and remote access. Its Open FPGA architecture enables full customization of acquisition logic via CAEN’s Sci-Compiler, with a graphical environment accessible to users with no VHDL experience.
It is also fully compatible with WaveDump2 and CoMPASS, supporting both advanced analysis and straightforward configuration. Whether for R&D, prototyping, or education, the DT5571 delivers reliable performance and flexibility in a compact, lab-friendly solution.
The DT5571 is available in desktop version and is ready to support your next acquisition challenge.
In collaboration with Nuclear Instruments.
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Technical Specifications
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GENERAL |
Form Factor: Desktop 257 x 102 x 331 mm3 (WxHxD) |
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ANALOG INPUT |
Channels: 1 BNC type Impedance: 50 Ω/1 kΩ programmable Bandwidth: 60 MHz, Programmable DC offset adjustment on each input in the full scale range Analog Coarse Gain: [x1:x100] Full Scale Range: [0.015 Vpp: 1.5 Vpp] |
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DIGITAL I/Os |
USER IO 0…2 (LEMO)
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DIGITAL CONVERSION |
Resolution: 14 bits Sampling Rate: 200 MS/s |
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CLOCK GENERATION |
200 MHz ADC clock Clock sources: internal/external
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TRIGGER |
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SYNCHRONIZATION |
Clock Propagation: USER I/Os connectors SYNC Connector Acquisition Synchronization
Sync connector allows to cascade multiple units and synchronize them with a single standard CAT5e cable |
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FPGA |
Open FPGA: Xilinx Zynq-7000 SoC Z-7030 |
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MEMORY |
1 GByte of memory for list readout on each SoC Up to 8kS/ch for simultaneous waveform readout |
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COMMUNICATION INTERFACE |
The different readout interface allows to integrate the DT5560SE in existing experimental environment.
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FIRMWARE |
Default
Custom
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FIRMWARE UPGRADE |
Firmware can be upgraded via Ethernet, mini-USB or JTAG mini-USB debugger (on-the-fly) |
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SOFTWARE |
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POWER REQUIREMENTS |
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