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Dual triggered gate generator
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Manual or pulse triggered START (NIM, TTL or ECL)
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Monostable (re-trigger) or bistable operation
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NIM, TTL and ECL output pulses from 50 ns to 10 s
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Manual or pulse triggered RESET
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(NIM, TTL and ECL) END-MARKER pulse
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VETO input
The CAEN Mod. V993C Dual Timer is a 2-unit VME module housing two identical triggered pulse generators.
The module produces NIM/TTL (NIM/TTL selection is performed via an on-board switch) and ECL pulses whose width ranges from 50 ns to 10 s when triggered. Output pulses are provided normal and negated.
Timers can be re-triggered with the pulse end marker signal, a short pulse occurring at the end of each output pulse.
The coarse adjustment of the output width is provided via a 9-position rotary switch, the fine adjustment can be performed via either 15 turn dial handle (with lock) or by providing an external voltage.
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LEMO connector 2-unit wide VME 6U for Mod. V993C |
Consult our connectors reference page for technical information.
The trigger START can be provided via either an external signal (NIM, TTL or ECL) or manually via a front panel switch.
The module features also VETO and RESET input signals.
RESET is also available on a front panel switch.
The V993C is equipped with LEMO 00 connectors for NIM/TTL signals and male pin couples for ECL signals.
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Compare
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Image
|
Name
|
Package
|
No. Of Sections
|
Function
|
Inputs per Section
|
Outputs per Section
|
Output Width/Delay
|
In Conn.
|
Out Conn.
|
|
|
V993C |
VME 2U |
2 |
Timer |
1 NIM/TTL + 1 ECL |
2+/1 NIM/TTL+ 1 ECL |
50 ns ÷ 10 s |
LEMO / Pin couple |
LEMO / Pin couple |
|
|
DT993 |
Desktop |
2 |
Timer |
1 NIM/TTL + 1 ECL |
2+/1 NIM/TTL+ 1 ECL |
50 ns ÷ 10 s |
LEMO / Pin couple |
LEMO / Pin couple |
|
|
V972 |
VME |
1 |
Delay |
1 Analog |
1 Analog |
2.6 ÷ 34.1 ns |
LEMO |
LEMO |
|
|
N93B |
NIM |
2 |
Timer |
1 NIM + 1 ECL |
2+/1 NIM+ 1 ECL |
50 ns ÷ 10 s |
LEMO / Pin couple |
LEMO / Pin couple |
Technical Specifications
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Packaging |
2U-wide VME unit |
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Output / Section |
OUT: NIM/TTL signal with a Fan-Out of 2, ECL signal |
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Output width |
50 ns ÷ 10 s (NIM, TTL and ECL) |
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WSET (width set voltage) |
0 ÷ 5 V d.c. |
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START/OUT delay |
<25 ns |
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RESET delay |
~30 ns: the timing cycle stops ~30 ns after the RESET pulse is sent |
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Rise/Fall Time |
<2 ns |
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Thermal stability |
-60 ppm/°C |
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