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128 channels, 14-bit @125 MS/s Digitizer
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Single-ended inputs with advanced programmable Front-End
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Based on powerful Xilinx Zynq-7000 SoC with open FPGA
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Full-featured readout system for the readout of large arrays of detector (PMTs, segmented HPGe, Gas Tubes, …)
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3U, 19” Rackmount unit with automatic fan control
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Fully supported by SCI-Compiler for easy FPGA programming (Firmware runtime license included onboard)
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Board-to-board synchronization with a single CAT5e cable.
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Configurable digital I/Os to interface with external systems
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Maximum flexibility: USB3.0, Ethernet, and optional Optical Link connectivity, to support remote management as well as extreme fast data flow
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2.4” touch screen display for quick configuration and status control
The CAEN Mod. R5560SE is a 3U, 19″ rack-mount 128 Channels 14-bit 125 MS/s Open FPGA Digitizer with Single-Ended inputs, designed to attain programmable data processing capabilities.
The R5560SE is designed for the readout of large arrays of detectors (PMTs, segmented HPGe, 3He tubes, …) using a customizable platform and an advanced programmable front-end. In fact, it is possible to take advantage of the powerful SoC mounted onboard to write a custom pulse processing algorithm on the open FPGA as well as build a middleware/software that fits the needs of the application of interest. Moreover, the advanced Front-End allows to easily connect and manage most of the detectors commonly used in Physics Experiments.
The board can manage simultaneously a large number of digital (LVDS, NIM, TTL) and analog signals, allowing to implement many functionalities required by physics experiments: signal digitization, complex trigger logic, Pulse Height Analysis with MCA capabilities, Time Tagging, Pulse Shape Discrimination, etc.
It is an optimal solution for large experiments, usually requiring fast digitization of analog signals and usage of several digital lines to interface with external systems. The board supports multi-board synchronization through a single CAT5e cable, with the possibility scale up to thousands of channels. Moreover, the rack-mount form factor simplifies the experimental setup in case of multi-board systems, where an effective space management is often a constraint.
SCI-Compiler software, the CAEN block-diagram-based firmware generator and compiler, helps in programming the FPGA to develop intensive real-time data processing.
A free and open-source demo readout software is available to manage the standard pulse height analysis firmware implementing energy measurements using a trapezoidal filter.
Applications includes:
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Charge integration for the readout of SiPM, Silicon Detectors, PMTs
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Neutron detectors readout
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Trapezoidal filter PHA for HPGe readout
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Pulse shape discrimination
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Continuous reset or transistor reset preamplifier readout
Developed in collaboration with Nuclear Instruments.
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Technical Specifications
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General |
Form Factor: 19”, 3U Rack-mount |
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DIMENSIONS (H/W/L) |
132.5/482.0/366.0 (399.8 with handles) |
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POWER REQUIREMENTS |
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ANALOG INPUT |
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DIGITAL I/Os |
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USER I/Os |
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DIGITAL CONVERSION |
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CLOCK GENERATION |
125 MHz ADC clock Clock sources: internal/external
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TRIGGER |
Trigger Source:
Trigger Time Stamp:
Trigger Propagation: Through USER I/Os and Sync Connector |
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SYNCHRONIZATION |
Sync connector allows to cascade multiple units and synchronize them with a single standard CAT5e cable |
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Open FPGA |
4x Xilinx Zynq-7000 SoC: |
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MEMORY |
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COMMUNICATION INTERFACE |
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FIRMWARE |
Default: Waveform recording and Pulse Height Analysis (Ethernet communication) |
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SOFTWARE |
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