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R5560SE

128 Channel 14 bit 125 MS/s Open FPGA Digitizer

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Home Digitizer FamiliesDigitizers 2.0 - Open FPGA14-bit 125 MS/s R5560SE

128 channels, 14-bit @125 MS/s Digitizer
Single-ended inputs with advanced programmable Front-End
Based on powerful Xilinx Zynq-7000 SoC with open FPGA
Full-featured readout system for the readout of large arrays of detector (PMTs, segmented HPGe, Gas Tubes, …)
3U, 19” Rackmount unit with automatic fan control
Fully supported by SCI-Compiler for easy FPGA programming (Firmware runtime license included onboard)
Board-to-board synchronization with a single CAT5e cable.
Configurable digital I/Os to interface with external systems
Maximum flexibility: USB3.0, Ethernet, and optional Optical Link connectivity, to support remote management as well as extreme fast data flow
2.4” touch screen display for quick configuration and status control

The CAEN Mod. R5560SE is a 3U, 19″ rack-mount 128 Channels 14-bit 125 MS/s Open FPGA Digitizer with Single-Ended inputs, designed to attain programmable data processing capabilities.

The R5560SE is designed for the readout of large arrays of detectors (PMTs, segmented HPGe, ³He tubes, …) using a customizable platform and an advanced programmable front-end. In fact, it is possible to take advantage of the powerful SoC mounted onboard to write a custom pulse processing algorithm on the open FPGA as well as build a middleware/software that fits the needs of the application of interest. Moreover, the advanced Front-End allows to easily connect and manage most of the detectors commonly used in Physics Experiments.

The board can manage simultaneously a large number of digital (LVDS, NIM, TTL) and analog signals, allowing to implement many functionalities required by physics experiments: signal digitization, complex trigger logic, Pulse Height Analysis with MCA capabilities, Time Tagging, Pulse Shape Discrimination, etc.

It is an optimal solution for large experiments, usually requiring fast digitization of analog signals and usage of several digital lines to interface with external systems. The board supports multi-board synchronization through a single CAT5e cable, with the possibility scale up to thousands of channels. Moreover, the rack-mount form factor simplifies the experimental setup in case of multi-board systems, where an effective space management is often a constraint.

SCI-Compiler software, the CAEN block-diagram-based firmware generator and compiler, helps in programming the FPGA to develop intensive real-time data processing.

A free and open-source demo readout software is available to manage the standard pulse height analysis firmware implementing energy measurements using a trapezoidal filter.

Applications includes:

Charge integration for the readout of SiPM, Silicon Detectors, PMTs
Neutron detectors readout
Trapezoidal filter PHA for HPGe readout
Pulse shape discrimination
Continuous reset or transistor reset preamplifier readout

Developed in collaboration with Nuclear Instruments.

Ordering Options

Code	Description
WR5560SEBXAA	R5560SEB 128 Ch. 14 bit 125 MS/s Digitizer single-ended-7035	RoHS
WR5560SEXAAA	R5560SE 128 Ch. 14 bit 125 MS/s Digitizer single-ended	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New R5560SE	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	MCX	n. a.	YES
	DT5560SE	Desktop	32	125	60	2	14	max. 8k	LEMO	basic PHA	YES

Image	Name	Analog Input	Connectors	Detector Frontend	Power Supply for Detector	Sampling Rate	Programmable Digital I/Os	Open FPGA	Communication Interface	Touchscreen Display	Readout Software	SCI-Compiler Software	Form Factor
	New R5560	128	RJ45	No	No	14-bit @ 125 MS/s	128 + 6	Xilinx Zynq-7000 SoC	USB 3.0, Optical Link, Ethernet	Yes	Yes	Included	Rack
	New R5560SE	128	MCX	Programmable	No	14-bit @ 125 MS/s	128 + 6	Xilinx Zynq-7000 SoC	USB 3.0, Optical Link, Ethernet	Yes	Yes	Included	Desktop
	DT5550	32	VHDCI	DT5550AFE available for single-ended detectors	No	14-bit @ 80 MS/s	48	Xilinx Kintek-7	USB 3.0	No	Yes	Included	Desktop
	DT5560SE	32	LEMO	Programmable	No	14-bit @ 125 MS/s	32+ 6	Xilinx Zynq-7000 SoC	Micro-USB, Optical Link, Ethernet	Yes	Yes	Included	Desktop
	DT5550W	Up to 128	Input for SipM	Weeroc ASIC	20 - 85 V	ASIC internal ADC or external ADC 14-bit @ 80 MS/s	8	Xilinx Kintek-7	USB 3.0	No	Yes	Included	Desktop


General	Form Factor: 19”, 3U Rack-mount Dimensions: 132.5/482.0/366.0 (399.8 with handles) mm
DIMENSIONS (H/W/L)	132.5/482.0/366.0 (399.8 with handles)
POWER REQUIREMENTS	Voltage: 100-240 V_ac ± 10% Frequency: 50/60 Hz Typ. Power consumption: 0.5 A @ 220 V_ac Fuse: 2.5A, 250V – 5 mm x 20 mm
ANALOG INPUT	Channels: 128 single-ended inputs on MCX Impedance: 50 Ω/1 kΩ programmable Bandwidth: 60 MHz Full Scale Range: [0.015 V_pp: 1.5 V_pp] Analog Coarse Gain: [x1:x100] Programmable DC offset adjustment on each input in the full scale range
DIGITAL I/Os	Channels: 4 x 32 Differential, 4 x 64 Single Ended Impedance: Z_diff = 100/50 Ω Connector: 4x VHDCI Coupling: DC Signal Type: LVCMOS 2.5V, LVDS, BLVDS
USER I/Os	Impedance: Z_diff = 100/50 Ω Coupling: DC
DIGITAL CONVERSION	Resolution: 14 bits Sampling Rate: 125 MS/s Simultaneously on each channel
CLOCK GENERATION	125 MHz ADC clock Clock sources: internal/external Internal 25 MHz oscillator External 25 MHz – USER IN 0 or SYNC connector
TRIGGER	Trigger Source: Internal/External: managed by the default firmware Complex trigger logic: implementable by the user on the open FPGA Trigger Time Stamp: Default FW: 32-bit counter, 8 ns resolution, 26-day range Custom FW: defined by the firmware design Trigger Propagation: Through USER I/Os and Sync Connector
SYNCHRONIZATION	Clock Propagation; USER I/Os connectors, SYNC Connector Acquisition Synchronization: Through programmable LEMO, Through dedicated SYNC Connector Sync connector allows to cascade multiple units and synchronize them with a single standard CAT5e cable
Open FPGA	4x Xilinx Zynq-7000 SoC: Z-7030 (R5560A, R5560SEA) Z-7035 model (R5560B, R5560SEB)
MEMORY	1 GByte of memory for list readout on each SoC Up to 8kS/ch for simultaneous waveform readout
COMMUNICATION INTERFACE	Ethernet (readout): 4 x 1Gbps (4 Gbps cumulative speed). Ethernet (slow control): 1 Gbps (slow control is an additional port, not required if the fast readout ethernet is used). Optical Link: Slots for 8 x 10Gbps SFP+ transceivers (communication protocol not implemented by default). USB 3.0: 1x USB 3.0 readout. All readout interfaces allow to perform the same task at different speed and using different media. They can be used independently or simultaneously. The different readout interface allows to integrate the R5560SE in existing experimental environment. PARALLEL TTL/LVDS Readout: Readout through the VHDCI digital I/O on custom protocol.
FIRMWARE	Default: Waveform recording and Pulse Height Analysis (Ethernet communication) Custom: Use SCI-Compiler to develop your own firmware. Firmware can be upgraded via Ethernet or USB 2.0 debugger (on-fly)
SOFTWARE	SCI-55X0 Readout Software to manage the default firmware SCI-Compiler for custom firmware development

R5560SE

128 Channel 14 bit 125 MS/s Open FPGA Digitizer

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R5560

R5560SE

DT5560SE

R5560

R5560SE

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DT5550W

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R5560SE

128 Channel 14 bit 125 MS/s Open FPGA Digitizer

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Sci-Compiler

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