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25 ps LSB
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21 bit resolution
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52 µs full scale range
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ECL/LVDS Input Signals
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5 ns Double Hit Resolution
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Trigger Matching and Continuous Storage acquisition modes
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Leading and/or Trailing Edge detection
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32 k x 32 bit output buffer
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MBLT, CBLT and 2eSST data transfer
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Multicast commands
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Geographical address supported
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Live Insertion
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Libraries, Demos (C and LabView) and Software tools for Windows and Linux
The CAEN Mod. V1290A-2eSST is a 32 channel Multihit TDC, housed in a 1-unit wide VME64X 6U module. The unit features High Performance Time to Digital Converter chips developed by CERN. LSB is 25 ps (21 bit resolution, 52 µs FSR). The module accepts both ECL and LVDS inputs.
The channels can be enabled for the detection of hits rising/falling edges. For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in “Events” (“Trigger Matching Mode”, with a programmable time window) or in “Continuous Storage Mode”. The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes.
The board houses a 32 k x 32 bit deep Output Buffer, that can be readout via VME in a completely independent way from the acquisition itself. The device supports MBLT, CBLT and 2eSST readout modes. Live insertion is also supported.
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Technical Specifications
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Packaging |
6U-high, 1U-wide VME unit |
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Inputs |
32 ECL / LVDS inputs, 110 Ohm impedance |
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Double hit resolution |
5 ns |
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Acquisition modes |
Trigger Matching Mode; Continuous Storage Mode |
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Built-in memory |
32 kwords deep Output Buffer |
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LSB |
25 ps |
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Dynamic Range |
52 μs |
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RMS resolution (with compensation enabled) |
32 ps (typical) |
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Integral non linearity (with compensation enabled) |
< 2.5 LSB |
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Max. differential non linearity (with compensation diabled) |
< 3 LSB |
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Interchannel Isolation |
≤3 LSB |
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Offset spread |
<2 ns |
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EXT TRIGGER input |
Two LEMO 00 bridged connectors, NIM signal, 50 Ω |
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Double Trigger resolution |
75 ns |
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Clock source |
Internal (40 MHz) or External (con Control connector), dip switch selectable |
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Control inputs |
active-high, differential ECL input signals:
rising-edge active, differential ECL input signals:
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Control outputs |
differential ECL output signal: |
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Displays |
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VME |
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