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V775

32 Channel Multievent TDC (35รท300 ps)

Datasheet

Home Modular Pulse Processing ElectronicsDigitalTDCs V775

Photo of V775
  • High channel density

  • 12 bit resolution

  • 5.7 ยตs / 32 ch conversion time

  • 600 ns fast clear time

  • Zero and overflow suppression for each channel

  • ยฑ0.1% integral non linearity

  • ยฑ1.5% differential non linearity

  • 32 event buffer memory

  • BLT32/MBLT64/CBLT32/CBLT64 data transfer

  • Multicast commands

  • Libraries, Demos (C and LabView) and Software tools for Windows and Linux

The CAEN Mod. V775 is a 1-unit wide VME 6U module housing 32 Time-to-Digital Conversion channels.
The Full Scale Range can be selected via VME from 140 ns to 1.2 ยตs with 8 bit resolution. The board can operate both in COMMON START and in COMMON STOP mode. Each time interval between the COM signal and the input signal is converted into a voltage level by the TAC sections. The outputs of the TAC sections are multiplexed and subsequently converted by two fast ADC modules (5.7 ยตs conversion time).

The integral non linearity is ยฑ0.1% of full scale range (FSR), measured from 2% to 97% of FSR; the differential non linearity is ยฑ1.5% of FSR, measured from 3% to 100% of FSR. The ADCs use a sliding scale technique to reduce the differential non-linearity.

Programmable zero suppression, multievent buffer memory, trigger counter and test features complete the flexibility of the unit. The module works in A24/A32 ADDRESS mode. The data transfer occurs in D16, D32, BLT32 or MBLT64 mode. The unit supports also the Chained Block Transfer (CBLT32/CBLT64) and the Multicast commands. The board supports the live insertion that allows inserting or removing them into the crate without switching it off.

Software

CAEN Toolbox

Multi-Functional Software Suite for the Upgrade of Front-end Boards, Bridges and Power Supplies

Accessories

A954

A954

Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm

Ordering Options

Code Description
WV775XACAAAA

V775AC โ€“ 32 Channel Multievent TDC (No JAUX No 12VDCDC, No live ins)

RoHS

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    Image
    Name
    Package
    No. of Channels
    Resolution (bit)
    Type
    Conversion Time (ยตs)
    LSB (ps)
    Full Scale Range (ยตs)
    Input Type
    Connectors
    VX1190A-2ESST

    VX1190A-2ESST

    VME64X

    128

    19 / 17

    Multihit Digital TDC

    -

    100 / 200 / 800

    52 / 104

    ECL / LVDS

    Robinson Nugent Flat

    DT5203

    DT5203

    Desktop

    64

    26

    Multihit Digital TDC

    -

    3.125

    52

    LVDS

    1 edge connector type HSEC8-170

    V1290A-2ESST

    V1290A-2ESST

    VME

    32

    21

    Multihit Digital TDC

    -

    25

    52

    ECL / LVDS

    Std. Flat

    V1290N-2ESST

    V1290N-2ESST

    VME

    16

    21

    Multihit Digital TDC

    -

    25

    52

    NIM

    LEMO

    V775N

    V775N

    VME

    16

    12

    Analog TDC

    2.8

    35 / 300

    0.14 / 1.2

    NIM

    LEMO

    A5203

    A5203

    Desktop

    64/128

    26

    Multihit Digital TDC

    -

    3.125

    52

    LVDS

    1 edge connector type HSEC8-170

    V775

    V775

    VME

    32

    12

    Analog TDC

    5.7

    35 / 300

    0.14 / 1.2

    ECL

    Std. Flat

    V1190A-2ESST

    V1190A-2ESST

    VME

    128

    19 / 17

    Multihit Digital TDC

    -

    100 / 200 / 800

    52 / 104

    ECL / LVDS

    Robinson Nugent Flat

    Technical Specifications

    Close

    Packaging

    1-unit wide 6U VME module (version AA requires the V430 backplane)

    Inputs

    32 ECL inputs, 110 ฮฉ impedance

    Full Scale Range

    VME programmable from 140 to 1200 ns (if sliding Scale is used FSR is reduced from 4095 to 3840 counts)

    Resolution

    12 bit

    LSB

    VME programmable from 35 to 300 ps

    RMS Noise

    0.8 counts typical, 2 counts maximum

    Integral non linearity

    ยฑ0.1% of FSR (measured from 5% to 95% of 3840 counts)

    Differential non linearity

    ยฑ1% (measured from 5% to 95% of 3840 counts)

    Interchannel Isolation

    > 66 dB

    Power rejection

    • 0.01 count/mV (+5V); 0.02 count/mV (-5V)
    • 0.005 count/mV (+12V); 0.001 count/mV (-12V)

    Fast clear time

    600 ns

    Conversion time

    5.7 ยตs for all channels

    Minimum Start/Stop delay

    • Common Start mode: 14 ns
    • Common Stop mode: 4 ns

    Zero suppression

    Threshold values programmable in:

    • 16 ADC counts steps over the entire FSR
    • 2 ADC counts steps over 1/8 of FSR

    GATE COMMON input

    Two LEMO 00 bridged connectors, NIM signal, high impedance
    Common Start/Stop signal

    Control inputs

    Active-high, differential ECL input signals:

    • RST: resets PEAK sections, MEB status and control registers
    • VETO: inhibits the conversion of the peaks
    • FCLR: FAST CLEAR of TAC sections
    • COM: Common Start/Stop signal

    Control outputs

    Differential ECL output signals:

    • DRDY: indicates the presence of data
    • BUSY: board full, resetting, converting or in MEMORY TEST mode

    VME interface

    • A24/A32
    • Geographical Addressing
    • Multicast commands
    • D16/D32,BLT21/MBLT64,CBLT32/CBLT64

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