DT5740D

32 Input Channel 12 bit 62.5MS/s Digitizer supporting DPP-QDC firmware

Home Modular Pulse Processing ElectronicsAnalogDigitizers DT5740D

12 bit 62.5 MS/s ADC
FPGA for real time Digital Pulse Processing::
- Digital Pulse Processing for Charge to Digital Converter (DPP-QDC)
32 or 16 input channels (single-ended)
High density input connectors, ERNI SMC Dual Row 68-pin (32 pairs)
MCX connectors (16 channels by using included auxiliary ERNI SMC Dual Row 68-pin connector)
2 Vpp input range
Sampling rate decimation factor
Trigger Time stamps
Multi-Event Memory buffer: 192 kS/ch divisible into up to 1024 buffers
Programmable event size and pre-post trigger adjustment
Programmable PLL onboard for clock synchronization with external systems or other DT5740D units
Optical Link interface (CONET proprietary protocol) Daisy-chainable through A5818 (PCIe Gen 3) Controller or A4818 (USB3-to-CONET)
USB 2.0 communication interface
Firmware upgradeable via USB/Optical Link
Fully supported by CoMPASS and WaveDump2 software

The CAEN Mod. DT5740D is a Waveform Digitizer, in Desktop form factor, housing 32 Input Channel 12 bit 62.5 MS/s Flash ADC, designed for waveform recording and supporting advanced algorithms for online digital pulse processing (DPP). The Digitizer is well suited for mid-slow signals generally coming from inorganic scintillators coupled with PMTs, gaseous detectors, and others. 32 input channels are available on ERNI SMC connectors, while 16 channels are optionally available also on MCX connectors.

The module features front panel Clock Input and a PLL for clock synthesis from internal/external references. The event acquisition takes place upon the trigger arrival in triggered mode for the waveform recording firmware (global trigger). Basically, the trigger source can be either external via the front panel connectors (single-ended), or by software command, or it can be locally generated thanks to self-trigger capability.

Due to the high input density, In the trigger domain, the inputs of the V1740D are managed as 8‐channel groups. The acquisition digital memory is a SRAM Multi-Event Buffer of 192 kS/ch divisible into 1 ÷ 1024 buffers of programmable size.

The DT5740D supports multi-board system building, allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple DT5740D boards.

The full communication with the DT5740D is possible either via the USB or Optical Link interface. The USB 2.0 interface allows for transfer rates up to 30 MB/s . The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability; therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A4818/A5818).

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C, Python, and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

CAEN Toolbox: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.

Waveform Recording Firmware compliant:

CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.
WaveDump2: Open source GUI-based application for the single and multi-board management of Digitizer 2.0 and 1.0 Series running the Waveform Recording / Scope firmware.

Digital Pulse Processing firmware for Physics Applications – this special firmware allows to perform on-line processing on detector signal directly digitizer:

DPP-QDC Pulse Processing for Charge to Digital Converter: DT5740D digitizer running DPP-QDC firmware becomes a digital replacement of Single Gate QDC plus Discriminator and Gate Generator.
CoMPASS: Multiparametric DAQ Software for Physics Applications with single and multi-board support of Digitizer 2.0 and 1.0 Series running the DPP firmware.

Ordering Options

Code	Description
WDT5740DXAAA	DT5740D – 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kSch, EP3C40, SE	RoHS

Add to Wishlist

Request a Quote

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	V1740	VME	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO

GENERAL

Weight: 675 g
Form Factor: Desktop
Dimension: 154x50x164 mm³ (WxHxD)

ANALOG INPUT

Number of Inputs: 32, single-ended, DC coupled
Bandwidth (-3dB): 30 MHz
Impedance: 50 Ω
Connector: ERNI SMC Dual Row 68pin
Full Scale Range: 2 Vpp
16-bit programmable DC offset adjustment in the full range independently on each channel
Abs. Max. Voltage Rating: 6 Vpp (with Vrail max +6 V or –6 V for any DAC offset value)

DIGITAL CONVERSION

Resolution: 12 bits
Sampling Rate:
- 62.5 MS/s simultaneously on each channel (nominal)
- Down to 488 kS/s by decimation function (Waveform Recording firmware only)

SYSTEM PERFORMANCE

ENOB: 11.20 (48 kS Buffer)
SINAD: 69.20 dB (48 kS Buffer, open input)
THD: 87.10 dB
SFDR: 94.9 dB
SIGMA: 0.50 LSB rms

DIGITAL I/O

TRG-IN/GPO/GPI
General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, veto, busy, etc.) TRG-IN/GPI: Zin = 50 Ω (internally terminated) GPO requires Rt = 50 Ω

ACQUISITION MEMORY

192k sample/ch (3 ms @ 62.5 MS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre/post-trigger

COMMUNICATION INTERFACE

USB	Optical Link
USB 2.0 compliant Transfer Rate: up to 30 MB/s	CAEN proprietary CONET protocol Transfer Rate: up to 80 MB/s Daisy Capability: up to 8 ADC modules per single optical link by A5818 Controller or A4818 Adapter

TRIGGER AND EVENT ACQUISITION

Triggered Mode

Trigger Sources

Trigger Timestamp – Waveform Rec. firmware

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals. In the trigger domain, the inputs of the DT5740 are managed as 8‐channel groups.

Software by register writing
External upon the leading edge of The TRG-IN signal (TTL/NIM)
Local (self-trigger) upon the channel discriminator with programmable threshold

Resolution: 16 ns
Counter range: 31 bits (default); extendable to 48-bit by firmware
Full-scale range: ~ 17 s @31-bit

Trigger Timestamp – DPP firmware

DPP-QDC:

Resolution: 16 ns
Counter Range: 32 bits (default); extendable to 48 -bit by firmware, to 64-bit by software
Full-scale range: ~ 68 s @32-bit

SYNCHRONIZATION

Clock Generation

CLK-IN Connector

By default, the Digitizer’s main clocks are generated upon a 50MHz reference frequency that can optionally be internal (50MHz local Oscillator) or external (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

Reference clock differential signal
2.54mm 3-pin AMPMODU Mod II male connector
AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)

Clock Synchronization

Default 50MHz frequency distributed by:

Fan-in into CLK-IN (DT4700)

PLL programming files for supported custom frequencies can be generated and loaded by the CAEN Toolbox software.

Data Synchronization

Programmable Busy/Veto logic on single-ended NIM/TTL I/O for event building (external hardware required).

Run Synchronization (Acqusition Start/Stop)

Optionally, by Daisy chain or fan-in propagation through single-ended TRG-IN/GPO/GPI connectors (NIM/TTL).

Trigger Distribution

Optionally, by Daisy chain or fan-out propagation through single-ended TRG-IN/GPO connectors, NIM/TTL (global trigger).

FPGA

Altera Cyclone EP1C16
One FPGA serves 16 channels

CAEN FIRMWARE

DPP Firmware (Shareware)

Waveform Recording Firmware (Freeware)

Upgrades (Free)

Pay firmware implementing a digital pulse processing algorithm:

DPP-QDC: Charge to Digital Converter

Designed for waveform recording.

Web available CFA files for Waveform Recording and DPP firmware upgrade through the CAEN Toolbox software, via USB or Optical Link.

SOFTWARE

Readout Software for Waveform Rec. Firmware (Freeware)	Readout Software for DPP Firmware (Freeware)	SDK and Tools (Freeware)
CAEN WaveDump: Digitizer 1.0 series support, single-board management, user-customizable WaveDump2: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based	CoMPASS: support for DPP-PHA of Digitizer 1.0 and 2.0 series, single and multi-board management, GUI based	General-purpose libraries (C/Python, LabVIEW) with demo samples for host Windows® and Linux® PC.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER CONSUMPTIONS

1.9 A @ +12 V DC (Typ.)
AC‐DC 12 V / 45 W power unit included

DT5740D

32 Input Channel 12 bit 62.5MS/s Digitizer supporting DPP-QDC firmware

Software

CAEN Toolbox

CAENDigitizer Library

COMPASS

WaveDump

CAEN FELib Library

WAVEDUMP2

DPP-QDC

Firmware

D-WAVE

Accessories

A318

A317

A3818

A746E

A371

AI2700

A654

A659

Ordering Options

You also may be interested in…

A4818

A5818

V1740D

VX1740D

Request a Quote

Compare

Technical Specifications

Footer

About Us

Resources

Applications

Support

News

Contact Us

Login