Digitizers

Analog

Photo of Digitizers

The Digitizers family provides high-performance waveform acquisition and real-time digital pulse processing platforms for nuclear physics, radiation detection, and advanced instrumentation. Available in desktop, VME, and modular form factors, these systems combine high-speed ADC front-ends with FPGA-based processing to enable both raw waveform capture and on-board extraction of energy, timing, and pulse-shape parameters. Architectures span Flash-ADC and switched-capacitor designs, with sampling rates from tens of MS/s up to multi-GS/s and resolutions from 10- to 14-bit, supporting applications from spectroscopy to fast timing and medical imaging.

Acquisition can operate in synchronous common-trigger mode or fully independent self-trigger mode for trigger-less systems. Data is stored in on-board memory (SRAM or DDR4 depending on generation) with configurable event size, pre/post-trigger windows, and multi-event buffering. Real-time Digital Pulse Processing (DPP) firmware enables parameter extraction such as energy, timestamp, charge, and pulse-shape discrimination, while optional open-FPGA architectures allow user-defined algorithms and custom logic.

The latest architectures integrate high-throughput readout via USB 3.0, optical link, or 1/10 GbE, embedded ARM processors for local control and automation, and simplified multi-board synchronization through clock and trigger distribution. Extensive software support—including configuration tools, libraries, and development frameworks—ensures seamless integration into complex DAQ systems across research, medical, and industrial environments.

  • High-speed waveform digitization with Flash-ADC or switched-capacitor architectures (up to multi-GS/s)

  • Real-time Digital Pulse Processing (energy, timing, PSD, charge) with selectable firmware

  • Flexible acquisition: common-trigger, independent self-trigger, and trigger-less operation

  • High-throughput readout via USB, optical link, VME, or 1/10 GbE with multi-board synchronization

  • Open FPGA and embedded ARM options for custom algorithms and autonomous operation

Digitizers Models

Grid Compare
V1725 / V1725S

V1725 / V1725S

  • 14 bit 250 MS/s ADC

  • FPGA for real time Digital Pulse Processing

    • Pulse Height Analysis (DPP-PHA)

    • Pulse Shape Discrimination (DPP-PSD)
DT2745

DT2745

  • 16-bit @ 125 MS/s ADC

  • 64 analog inputs, differential or single-ended, on four 2mm 40-pin header connectors

  • Software selectable Analog Gain up to x100
R5560
New

R5560

  • 128 channels, 14-bit @125 MS/s Digitizer

  • Based on powerful Xilinx Zynq-7000 SoC with open FPGA

  • 2U, 19” Rackmount unit with automatic fan control
DTL2730
New

DTL2730

  • 8 independent input channels, 500 MS/s 14-bit, with individual DC offset adjustment

  • Front panel readout via USB-3.0 or 1Gb Ethernet

  • Based on Kintex UltraScale+ FPGA
V1761

V1761

  • 10 bit 4 GS/s ADC

  • 2 inputs channels, single-ended

  • 1 Vpp input range
DT5751

DT5751

  • 10 bit 1 GS/s (2 GS/s in DES mode) ADC

  • FPGA for real-time data processing:

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Length Encoding (DPP-ZLEplus)
VX1740D

VX1740D

  • 12 bit 62.5 MS/s ADC

  • FPGA for real-time data processing:

    • Digital Charge to Digital Converter (DPP-QDC)

    • 64 input channels (single-ended)
DT5725 / DT5725S

DT5725 / DT5725S

  • 14 bit 250 MS/s ADC

  • FPGA for real time Digital Pulse Processing

    • Pulse Height Analysis (DPP-PHA)

    • Pulse Shape Discrimination (DPP-PSD)
VX1724

VX1724

  • 14 bit 100 MS/s ADC

  • FPGA for real time Digital Pulse Processing::

    • Pulse Height Analysis (DPP-PHA)

    • Dynamic Acquisition Window (DPP-DAW)
DT5761

DT5761

  • 10 bit 4 GS/s ADC

  • 1 input channel, single-ended

  • 1 Vpp input range
VX2745

VX2745

  • 64 independent input channels, 125 MS/s 14-bit, with individual DC offset adjustment and Software selectable analog gain (VGA)

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
DT5724

DT5724

  • 14 bit 100 MS/s ADC

  • FPGA for real time Digital Pulse Processing::

    • Pulse Height Analysis (DPP-PHA)

    • Dynamic Acquisition Window (DPP-DAW)
DT5730 / DT5730S

DT5730 / DT5730S

  • 14 bit 500 MS/s ADC

  • FPGA for real time Digital Pulse Processing

    • Pulse Height Analysis (DPP-PHA)

    • Pulse Shape Discrimination (DPP-PSD)
VX2740

VX2740

  • 64 independent input channels, 125 MS/s 16-bit, with individual DC offset adjustment

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
V1724

V1724

  • 14 bit 100 MS/s ADC

  • FPGA for real time Digital Pulse Processing:

    • Pulse Height Analysis (DPP-PHA)

    • Dynamic Acquisition Window (DPP-DAW)
VX1761

VX1761

  • 10 bit 4 GS/s ADC

  • 2 inputs channels, single-ended)

  • 1 Vpp input range
DT2740

DT2740

  • 64 independent input channels, 125 MS/s 16-bit, with individual DC offset adjustment

  • Front panel readout via USB-3.0 or 1Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
V2740

V2740

  • 64 independent input channels, 125 MS/s 16-bit, with individual DC offset adjustment

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
DT2751
New

DT2751

  • 16 independent input channels, 1 GS/s 14-bit, with individual DC offset adjustment and Software selectable analog gain (VGA)

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
V1730 / V1730S

V1730 / V1730S

  • 14 bit 500 MS/s ADC

  • Analog inputs on MCX coaxial connectors

  • NSCLDAQ Supported (DPP-PSD and DPP-PHA only)
N6725 / N6725S

N6725 / N6725S

  • 8 channels, 14-bit @ 250 MS/s

  • Analog inputs on MCX coaxial connectors

  • 0.5 and 2 Vpp selectable input dynamic range with programmable DC offset adjustment
VX2751
New

VX2751

  • 16 independent input channels, 500 MS/s 14-bit, with individual DC offset adjustment and software selectable analog gain (VGA)

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
VX1740

VX1740

  • 12 bit 62.5 MS/s ADC

  • 64 input channels (single-ended)

  • High density input connectors, ERNI SMC Dual Row 68-pin (32 pairs)
DT5740D

DT5740D

  • 12 bit 62.5 MS/s ADC

  • FPGA for real time Digital Pulse Processing::

    • Digital Pulse Processing for Charge to Digital Converter (DPP-QDC)

    • 32 or 16 input channels (single-ended)
V2745

V2745

  • 16 bit @ 125 MS/s ADC

  • 64 analog inputs, differential or single-ended, on four 2mm 40-pin header connectors

  • Software selectable Analog Gain up to x100
DT5742

DT5742

  • 12 bit 5 GS/s ADC

  • Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)

    • 1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)

    • 5 GS/s , 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
VX1725 / VX1725S

VX1725 / VX1725S

  • 14 bit 250 MS/s ADC

  • FPGA for real time Digital Pulse Processing

    • Pulse Height Analysis (DPP-PHA)

    • Pulse Shape Discrimination (DPP-PSD)
VX2730

VX2730

  • 32 or 16 independent input channels, 500 MS/s 14-bit, with individual DC offset adjustment and Software selectable analog gain (VGA)

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
VX1730 / VX1730S

VX1730 / VX1730S

  • 14-bit @ 500 MS/s ADC

  • Analog inputs on MCX coaxial connectors

  • NSCLDAQ Supported (DPP-PSD and DPP-PHA only)
V2730B

V2730B

  • 16 independent input channels, 500 MS/s 14-bit, with individual DC offset adjustment and Software selectable analog gain (VGA)

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
N6730 / N6730S

N6730 / N6730S

  • 14-bit @ 500 MS/s

  • Analog inputs on MCX coaxial connectors

  • NSCLDAQ Supported (DPP-PSD and DPP-PHA only)
V1743

V1743

  • 12-bit @ 3.2 GS/s ADC

  • Switched Capacitor technology based on the SAMLONG chip (CEA/IRFU & CNRS/IN2P3/LAL Orsay)

    • 1024 capacitor cells per channel (acquisition window of ~ 320 ns @ 3.2 GS/s)

    • 3.2 GS/s , 1.6 GS/s, 800 MS/s, 400 MS/s software selectable sampling frequencies
VX1751

VX1751

  • 10 bit 1 GS/s (2 GS/s in DES mode) ADC

  • FPGA for real-time data processing:

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Length Encoding (DPP-ZLEplus)
DT5740

DT5740

  • 12 bit 62.5 MS/s ADC

  • 32 or 16 input channels (single-ended)

  • High density input connectors, ERNI SMC Dual Row 68-pin (32 pairs)
V1720

V1720

  • 12 bit 250 MS/s ADC

  • FPGA for real time Digital Pulse Processing:

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Suppression (Waveform Recording Firmware)
V1751

V1751

  • 10 bit 1 GS/s (2 GS/s in DES mode) ADC

  • FPGA for real-time data processing:

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Length Encoding (DPP-ZLEplus)
VX1742

VX1742

  • 12 bit 5 GS/s ADC

  • Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)

    • 1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)

    • 5 GS/s , 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
DT5743

DT5743

  • 12-bit @ 3.2 GS/s ADC

  • Switched Capacitor technology based on the SAMLONG chip (CEA/IRFU & CNRS/IN2P3/LAL Orsay)

    • 1024 capacitor cells per channel (acquisition window of ~ 320 ns @ 3.2 GS/s)

    • 3.2 GS/s , 1.6 GS/s, 800 MS/s, 400 MS/s software selectable sampling frequencies
DT5720

DT5720

  • 12 bit 250 MS/s ADC

  • FPGA for real time Digital Pulse Processing:

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Suppression (Waveform Recording Firmware)
V1742

V1742

  • 12 bit 5 GS/s ADC

  • Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)

    • 1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)

    • 5 GS/s , 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
DT2730

DT2730

  • 32 or 16 independent input channels, 500 MS/s 14-bit, with individual DC offset adjustment and Software selectable analog gain (VGA)

  • Front panel readout via USB-3.0 or 1/10Gb Ethernet

  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
VX1743

VX1743

  • 12-bit @ 3.2 GS/s ADC

  • Switched Capacitor technology based on the SAMLONG chip (CEA/IRFU & CNRS/IN2P3/LAL Orsay)

    • 1024 capacitor cells per channel (acquisition window of ~ 320 ns @ 3.2 GS/s)

    • 3.2 GS/s , 1.6 GS/s, 800 MS/s, 400 MS/s software selectable sampling frequencies
V1740D

V1740D

  • 12 bit 62.5 MS/s ADC

  • FPGA for real-time data processing:

    • Digital Charge to Digital Converter (DPP-QDC)

    • 64 input channels (single-ended)
DTL2751
New

DTL2751

  • 4 independent input channels, 1 GS/s 14-bit, with individual DC offset adjustment

  • Front panel readout via USB-3.0 or 1Gb Ethernet

  • Based on Kintex UltraScale+ FPGA
VX1720

VX1720

  • 12 bit 250 MS/s ADC

  • FPGA for real time Digital Pulse Processing:

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Suppression (Waveform Recording Firmware)
N6742

N6742

  • 12 bit @ 5 GS/s, 1-unit wide NIM module

  • Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)

    • 1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)

    • 5 GS/s, 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
Image
Name
Package
No. of Channels
Max Sampling Rate (MS/s)
Bandwidth (MHz)
Full Scale Range (V)
Resolution (bits)
Board Memory (Samples/ch)
Analog Input Connectors
CAEN firmware
Open FPGA
V1725 / V1725S

V1725 / V1725S

VME

8 / 16

250

125

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE

NO
DT2745

DT2745

Desktop

64

125

20

[0.04 + 4]

16

21 M

2mm 40-pin header male

DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus(cs)

YES
R5560
New

R5560

rack mount 19 -2U

128+6

125

60

2

14

max. 8k

RJ45

n. a.

YES
DTL2730
New

DTL2730

Desktop

8

500

TBD

TBD

14

TBD

MCX

DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)

YES
V1761

V1761

VME

2

4000

1000

1

10

7.2 M / 57.6 M

MCX

D-WAVE

NO
DT5751

DT5751

Desktop

2(DES mode) - 4

2000(DES mode) - 1000

500

0.2 / 1

10

3.6 M(DES mode) - 1.8 M

MCX

DPP-PSD, DPP-ZLEplus, D-WAVE

NO
VX1740D

VX1740D

VME64X

64

62.5

30

2 / 10

12

192 k

SMC 68P

DPP-QDC, D-WAVE

NO
DT5725 / DT5725S

DT5725 / DT5725S

Desktop

8

250

125

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE

NO
VX1724

VX1724

VME64X

8

100

40

0.5 / 2.25 / 10

14

512 k / 4 M

MCX

DPP-PHA, DPP-DAW

NO
DT5761

DT5761

Desktop

1

4000

1000

1

10

7.2 M

MCX

D-WAVE

NO
VX2745

VX2745

VME64X

64

125

20

[0.4 ÷ 4]

16

21 M

2mm 40-pin header male

D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus(cs)

YES
DT5724

DT5724

Desktop

4 / 2

100

40

0.5 / 2.25 / 10

14

512 k / 4 M

MCX

DPP-PHA, DPP-DAW, D-WAVE

NO
DT5730 / DT5730S

DT5730 / DT5730S

Desktop

8

500

250

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE

NO
VX2740

VX2740

VME64X

64

125

50

2

16

21 M

2mm 40-pin header male

DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus(cs)

YES
V1724

V1724

VME

8

100

40

0.5 / 2.25 / 10

14

512 k / 4 M

MCX

DPP-PHA, DPP-DAW, D-WAVE

NO
VX1761

VX1761

VME64X

2

4000

1000

1

10

7.2 M / 57.6 M

MCX

D-SCOPE

NO
DT2740

DT2740

Desktop

64

125

50

2

16

21 M

2mm 40-pin header male

DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus(cs)

YES
V2740

V2740

VME

64

125

50

2

16

21 M

2mm 40-pin header male

DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus(cs)

YES
DT2751
New

DT2751

Desktop

16

1000

500

[0.2 ÷ 2]

14

84 M

MCX

DPP-PHA, DPP-PSD, D-SCOPE(cs)

YES
V1730 / V1730S

V1730 / V1730S

VME

8 / 16

500

250

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE

NO
N6725 / N6725S

N6725 / N6725S

NIM

8

250

125

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE

NO
VX2751
New

VX2751

VME64X

16

1000

500

[0.2 ÷ 2]

14

84 M

MCX

DPP-PHA, DPP-PSD, D-SCOPE(cs)

YES
VX1740

VX1740

VME64X

64

62.5

30

2 / 10

12

192 k / 1.5 M

SMC 68P

D-WAVE

NO
DT5740D

DT5740D

Desktop

32(SMC conn.) - 16(MCX conn)

62.5

30

2 / 10

12

192 k

SMC 68P - MCX

DPP-QDC,D-WAVE

NO
V2745

V2745

VME

64

125

20

[0.04 + 4]

16

21 M

2mm 40-pin header male

DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus(cs)

YES
DT5742

DT5742

Desktop

16 + 1

5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)

500

1

12

0.128 / 1

MCX

D-WAVE

NO
VX1725 / VX1725S

VX1725 / VX1725S

VME64X

8 / 16

250

125

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE

NO
VX2730

VX2730

VME64X

32

500

250

[0.2 ÷ 4]

14

84 M

MCX

DPP-PHA, DPP-PSD, D-SCOPE(cs)

YES
VX1730 / VX1730S

VX1730 / VX1730S

VME64X

8 / 16

500

250

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE

NO
V2730B

V2730B

VME64

16

500

250

[0.2 ÷ 4]

14

MCX

84 M

DPP-PHA, DPP-PSD, D-SCOPE(cs)

YES
N6730 / N6730S

N6730 / N6730S

NIM

8

500

250

0.5 - 2

14

640 k / 5.12 M

MCX

DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE

NO
V1743

V1743

VME

16

3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)

500

2.5

12

0.007 M

MCX

D-WAVE

NO
VX1751

VX1751

VME64X

2(DES mode) - 4

2000(DES mode) - 1000

500

0.2 / 1

10

3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M

MCX

DPP-PSD, DPP-ZLEplus, D-WAVE

NO
DT5740

DT5740

Desktop

32(SMC conn.) - 16(MCX conn)

62.5

30

2 / 10

12

192 k

SMC 68P - MCX

D-WAVE

NO
V1720

V1720

VME

8

250

125

2

12

1.25 M / 10 M

MCX

DPP-PSD, D-WAVE

NO
V1751

V1751

VME

2(DES mode) - 4

2000(DES mode) - 1000

500

0.2 / 1

10

3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M

MCX

DPP-PSD, DPP-ZLEplus, D-WAVE

NO
VX1742

VX1742

VME64X

32 + 2

5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)

500

1

12

0.128 / 1

MCX

D-WAVE

NO
DT5743

DT5743

Desktop

8

3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)

500

2.5

12

0.007 M

MCX

D-WAVE

NO
DT5720

DT5720

Desktop

4 / 2

250

125

2

12

1.25 M / 10 M

MCX

DPP-PSD, D-WAVE

NO
V1742

V1742

VME

32 + 2

5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)

500

1

12

0.128 / 1

MCX

D-WAVE

NO
DT2730

DT2730

Desktop

32 / 16

500

250

[0.2 ÷ 4]

14

MCX

84 M

DPP-PHA, DPP-PSD, D-SCOPE

YES

VX1743

VX1743

VME64X

16

3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)

500

2.5

12

0.007 M

MCX

D-WAVE

NO
V1740D

V1740D

VME

64

62.5

30

2 / 10

12

192 k

SMC 68P

DPP-QDC, D-WAVE

NO
DTL2751
New

DTL2751

Desktop

4

1000

TBD

TBD

14

MCX

TBD

DPP-PSD(cs), D-SCOPE(cs)

YES
VX1720

VX1720

VME64X

8

250

125

2

12

1.25 M / 10 M

MCX

DPP-PSD, D-WAVE

NO
N6742

N6742

NIM

16 + 1

5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)

500

1

12

0.128 / 1

MCX

D-WAVE

NO