VX2751

• 16 differential pairs

• Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)

• LVDS

• Zdiff = 100 Ω (when set as inputs)

• 2.54mm 34-pin AMPMODU Mod II male connector

• General-purpose digital I/Os

• Sigle-ended TTL/NIM

• LEMO 00 male connector

• Software programmable function (trigger, veto, busy, etc.)

• TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω)

• TRG-OUT requires Rt = 50 Ω

• GPIO as Input must be terminated with 50 Ω

• GPIO as TTL Output requires Rt = 50 Ω

• GPIO as NIM Output requires Rt = 50 Ω or 25 Ω

1 GbE

• Copper RJ45 or optical LC connector on SFP+ transceiver

• Protocol: TCP

• Transfer rate: 110 MB/s

10 GbE ^{(Contact CAEN Support)}

• Copper RJ45 or LC optical connector on SFP+ transceiver

• Protocol: UDP

• Transfer rate: 850 MB/s

USB 3.0

• Connector Type: USB-C

• Protocol: USB 3.1 GEN1

• Transfer rate: 280 MB/s

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals; a zero suppression function is available.

• Software by register writing

• External upon the leading edge of The TRG-IN signal (TTL/NIM)

• Local (self-trigger) upon the channel discriminator with programmable threshold

• Resolution: 8 ns coarse time stamp

• Counter range: 48 bits

• Full-scale range: ~625 h

Streaming Readout Mode

Each channel autonomously identifies the ROI and uses the local trigger to get events independently on the other channels; validation logics can be configured for correlated acquisition (coincidence/anticoincidence).

Trigger Timestamp – DPP firmware

• Resolution: 1 ns coarse timestamp, 1 ps fine timestamp

• Counter range: 48 bits

• Full-scale range: ~78 h

Clock Generation

By default, the Digitizer’s main clocks can be optionally generated upon from the internal 50MHz or external 62.5MHz reference (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

CLK-IN/CLK-OUT Connector

• Two differential pairs:

  – CLK, reference clock signal

  – SYNC, synchronization signal (start/stop, T0, etc.)

• 2.54mm 4-pin AMPMODU Mod II male connector

• CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)

• CLK-OUT: LVDS

Clock Synchronization

Default 62.5MHz frequency distributed by:

• Fan-out to CLK-IN

• CLK-IN/CLK-OUT Daisy chain with sw programmable CLK-OUT delay shift

Custom frequencies can be supported upon request.

Data Synchronization

Programmable Busy/Veto logic on differential LVDS I/O, or single-ended NIM/TTL I/O for event building.

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-out propagation through differential CLK-IN/CLK-OUT or LVDS I/O, or single-ended NIM/TTL I/O.

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/O (global trigger) or LVDS I/O (global or local trigger).

Trigger Time Stamp Reset

Optionally, by Software from start run command or Hardware from S-IN/GPIO input (Scope Firmware only).

Pay firmware implementing a digital pulse processing algorithm:

• DPP-PSD: Charge Integration, Pulse Shape Discrimination, CFD for fine timestamp

30-minute per power cycle in Trial mode; license is required for full-time work.

Designed for waveform recording.

Web available CUP files for Scope and DPP firmware upgrade via Web Interface or CAEN Toolbox software.

Scope Personalization

Customizable features of the Scope firmware:

• Common trigger

• Simultaneous waveform recording management on all the input channels

• Trigger logic

• Wave processing

DPP Personalization

Customizable features of the DPP firmware:

• Individual trigger and channel acquisition management

• DPP algorithm

• Trigger logic

• Event data information

• CoMPASS spectroscopy software (DPP firmware only)

• WaveDump2 (Scope firmware only)

Automatic generation of drivers (USB, Ethernet), libraries, and demo software for Windows®, Linux®.

SDK and Tools (Freeware)

Web Interface

General-purpose libraries (C/Python) with demo samples for host Windows® and Linux® PC, and embedded Arm.

Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring.