VX2730

32/16 Input Channel 14 bit 500 MS/s Digitizer with Programmable Analog Gain

Home Digitizer FamiliesDigitizers 2.0 - Open FPGA14-bit 500 MS/s VX2730

32 or 16 independent input channels, 500 MS/s 14-bit, with individual DC offset adjustment and Software selectable analog gain (VGA)
Front panel readout via USB-3.0 or 1/10Gb Ethernet
On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
5GB of total acquisition memory (DDR4)
Open FPGA architecture fully supported by SCI-Compiler tool
Ready-to-Use Firmware solutions to get time-stamped waveforms and physical quantities (check here for the available options)
Triggered and Streaming Readout modes supported
System features: Multi-board synchronization, digital I/Os for trigger logic, on-board storage of multiple firmware images, 125MS/s 14-bit DAC output and integrated web interface
Software ecosystem:
- GUI-based readout software available for multiparametric spectroscopy (CoMPASS) or waveform recording (WaveDump2)
- Firmware/software generator and compiler for the Open FPGA (Sci-Compiler), eliminating the need for FPGA programming skills
- Libraries (FELib) and demo codes are provided for software customization
Wide range of applications (from Nuclear and Particle Physics to High Timing Resolution, Fast Neutron Spectroscopy, and Homeland Security)
Suited for signals from liquid or inorganic scintillators coupled to PMTs or SiPMs
Fully compliant with CAEN μ-crate module

The CAEN mod. VX2730 Digitizer is a 32 or 16 input channel digital signal processor for radiation detectors in the VME64X form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for a complete range of applications like nuclear and particle physics, high-timing resolution, Fast Neutron Spectroscopy, and Homeland Security. It is compliant with mid-fast signals typically coming from liquid or inorganic scintillators coupled to PMTs or SiPMs.

Each input channel is able to independently digitize detector signals through a 14-bit ADC at 500 MS/s. Data acquisition is driven by trigger signal generation and the identification of a Region of Interest (ROI), defined in terms of sample count or time duration. Trigger sources can be local (channel self-trigger), external, or software-based. Once acquired, the digitized data is processed within the FPGA, stored in high-speed memory as events—including Trigger ID and Timestamp tags—and then transferred via high-bandwidth communication interfaces for further analysis.

The digitizer supports different acquisition modes, designed to balance throughput, latency, and data efficiency according to experimental requirements:

Triggered Mode: All channels acquire data simultaneously upon a global trigger generated by a Central Logic Unit, which processes local triggers from individual channels. External and software triggers can also be configured as sources for the global trigger. Zero suppression algorithms can be applied to remove non-significant data and reduce the readout payload.
Streaming Readout Mode: Each channel autonomously identifies its ROI using the self-trigger mechanism, acquiring data independently of the other channels. This mode includes automatic zero suppression (non-triggered channels are not acquired), maximizes acquisition rates, and is ideal for applications requiring real-time parameter extraction. In addition, correlation logics can be configured to validate event acquisition upon coincidences or anticoincidences between local and external triggers.

The VX2730 can operate using both pre-configured firmware developed by CAEN and custom user-generated firmware, offering flexibility for a wide range of applications. Multiple firmware images can be stored simultaneously in the digitizer’s FLASH memory and quickly activated when needed. CAEN provides ready-to-use firmware solutions optimized for specific acquisition and processing needs:

Scope Firmware: Based on full waveform recording in triggered acquisition mode. A zero suppression function is available to reduce unnecessary data readout.
DPP-PSD Firmware: Implements Digital Pulse Processing algorithms for charge integration and pulse shape discrimination. Physical parameters such as pulse height, charge, timestamp, and PSD are extracted from waveforms acquired in streaming readout. It is yet possible to save both raw waves and parameters.

For users requiring custom acquisition and processing, the Open FPGA architecture enables firmware customization through SCI-Compiler. This graphical tool allows users to create personalized firmware solutions without HDL skills. In addition, Sci-Compiler automatically generates drivers and libraries and provides graphical utilities for developing custom DAQ software.

The Linux-based Arm processor embedded in the onboard CPU makes it possible to run automated user routines. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options. Multiple communication interfaces offer flexible readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet.

For detailed information on available firmware for the 2730 family and the structure of programming files (.CUP), please refer to the following page.

This product is compatible with the following third-party software:

PKUCAENDAQ

Moreover, you can check this FAQ to see which CAEN VME crates are suitable for this product.

Ordering Options

Code	Description
WVX2730BXAAA	VX2730B – 16 Ch. 14 bit 500MS/s Digitizer with Programmable Input Gain	RoHS
WVX2730XAAAA	VX2730 – 32 Ch. 14 bit 500MS/s Digitizer with Programmable Input Gain	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES

GENERAL

Weight: 700 g
Form Factor: 1-unit wide VMEX64
Dimension: 6U x 160 mm

ANALOG INPUT

Number of Inputs: 16 or 32, single-ended, DC coupled
Bandwidth (-3dB): 250 MHz guaranteed for Gain ≥ 2
Impedance: 50 Ω
Gain: x1 ÷ x20, software programmable in steps of 1 dB independently on each input channel
Connector Type: MCX
Full Scale Range: 4 Vpp ÷ 0.2 Vpp
DC Offset: Adjustable in the ± 2.5V range independently on each input channel

DIGITAL CONVERSION

Resolution: 14 bits
Sampling Rate: 500 MS/s (simultaneously on each input channel)

SYSTEM PERFORMANCE

ENOB (Typ.): 10.5 (@50MHz, -3dB, Gain x2)
RMS (Typ.): 2.4 LSB RMS (@Gain x2)

DIGITAL I/O

LVDS I/O	TRG-IN/TRG-OUT/GPIO/S-IN
16 differential pairs Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.) LVDS Zdiff = 100 Ω (when set as inputs) 2.54mm 34-pin AMPMODU Mod II male connector	General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, veto, busy, etc.) TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω) TRG-OUT requires Rt = 50 Ω GPIO as Input must be terminated with 50 Ω GPIO as TTL Output requires Rt = 50 Ω GPIO as NIM Output requires Rt = 50 Ω or 25 Ω

ANALOG OUT

Software programmable DAC output for signal inspection, pulse generation, majority level
14-bit Digital-to-Analog Converter (DAC)
125 MS/s Update Rate
LEMO 00 connector
±1 V @ 50Ω load
±2 V @ hi-Z load Output Range

ACQUISITION MEMORY

5 GB total DDR4 memory size (83.886 MS/ch) divisible in multiple buffers
Maximum record length: ~84 ms @ 500 MS/s (total memory size divided by 2)¹

¹_{Value referred to the Scope firmware (minimum of two buffers admitted)}

COMMUNICATION INTERFACES

1 GbE	10 GbE ⁽^Contact^{CAEN Support)}	USB 3.0
Copper RJ45 or optical LC connector on SFP+ transceiver Protocol: TCP Transfer rate: 110 MB/s	Copper RJ45 or LC optical connector on SFP+ transceiver Protocol: UDP Transfer rate: 850 MB/s	Connector Type: USB-C Protocol: USB 3.1 GEN1 Transfer rate: 280 MB/s

TRIGGER AND EVENT ACQUISITION

Triggered Mode

Trigger Sources

Trigger Timestamp – Scope firmware

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals; a zero suppression function is available.

Software by register writing
External upon the leading edge of The TRG-IN signal (TTL/NIM)
Local (self-trigger) upon the channel discriminator with programmable threshold

Resolution: 8 ns coarse time stamp
Counter range: 48 bits
Full-scale range: ~625 h

Streaming Readout Mode

Each channel autonomously identifies the ROI and uses the local trigger to get events independently on the other channels; validation logics can be configured for correlated acquisition (coincidence/anticoincidence).

Trigger Timestamp – DPP firmware

Resolution: 2 ns coarse timestamp, 2 ps fine timestamp
Counter range: 48 bits
Full-scale range: ~156 h

SYNCHRONIZATION

Clock Generation

By default, the Digitizer’s main clocks can be optionally generated upon from the internal 50MHz or external 62.5MHz reference (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

CLK-IN/CLK-OUT Connector

Two differential pairs:

– CLK, reference clock signal

– SYNC, synchronization signal (start/stop, T0, etc.)
2.54mm 4-pin AMPMODU Mod II male connector
CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
CLK-OUT: LVDS

Clock Synchronization

Default 62.5MHz frequency distributed by:

Fan-out to CLK-IN
CLK-IN/CLK-OUT Daisy chain with sw programmable CLK-OUT delay shift

Custom frequencies can be supported upon request.

Data Synchronization

Programmable Busy/Veto logic on differential LVDS I/O, or single-ended NIM/TTL I/O for event building.

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-out propagation through differential CLK-IN/CLK-OUT or LVDS I/O, or single-ended NIM/TTL I/O.

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/O (global trigger) or LVDS I/O (global or local trigger).

Trigger Time Stamp Reset

Optionally, by Software from start run command or Hardware from S-IN/GPIO input (Scope Firmware only).

FPGA

Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
Programmable logic with more than 1100K system logic cells and 80Mbit memory

CAEN FIRMWARE

Developed by CAEN, stored in the on-board FLASH memory, and live rebootable by Web Interface.

DPP Firmware (Shareware)

Scope Firmware (Freeware)

Upgrades (Free)

Pay firmware implementing a digital pulse processing algorithm:

DPP-PSD: Charge Integration, Pulse Shape Discrimination, CFD for fine timestamp
DPP-PHA: Pulse Height Analysis

30-minute per power cycle in Trial mode; license is required for full-time work.

Designed for waveform recording.

Web available CUP files for Scope and DPP firmware upgrade via Web Interface or CAEN Toolbox software.

USER FIRMWARE (OPEN FPGA)

Sci-Compiler (Shareware)

Pay graphical tool for User Firmware generation and compiling with CAEN Programmable Boards.

Scope Personalization

Customizable features of the Scope firmware:

Common trigger
Simultaneous waveform recording management on all the input channels
Trigger logic
Wave processing

DPP Personalization

Customizable features of the DPP firmware:

Individual trigger and input channel acquisition management
DPP algorithm
Trigger logic
Event data information

SOFTWARE

Readout SW for CAEN Firmware (Freeware)	SCI-Compiler for Open FPGA (Shareware)
CoMPASS spectroscopy software (DPP firmware only) WaveDump2 (Scope firmware only)	Automatic generation of drivers (USB, Ethernet), libraries, and demo software for Windows®, Linux®.
SDK and Tools (Freeware)	Web Interface
General-purpose libraries (C/Python) with demo samples for host Windows® and Linux® PC, and embedded Arm.	Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER REQUIREMENTS

+12V: 0.5 A (Typ.)
+5V: 4.8 A (Typ.)
+3.3V: 8.9 A (Typ.)

The values above are preliminary and referred to a 1-GbE Scope firmware; they are subject to change depending on the firmware type.

VX2730

32/16 Input Channel 14 bit 500 MS/s Digitizer with Programmable Analog Gain

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DTL2730

VX2730

V2730B

DT2730

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VX2730

32/16 Input Channel 14 bit 500 MS/s Digitizer with Programmable Analog Gain

Software

CAEN Toolbox

COMPASS

Sci-Compiler

CAEN FELib Library

WAVEDUMP2

Firmware

D-SCOPE

DPP-PSD

DPP-PHA

DPP-SUP

Accessories

A954

A316

A319A

A319B

A952

A953

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