DT2745

64 Channel 16 bit 125 MS/s Digitizer with Programmable Input Gain

Datasheet

Home Modular Pulse Processing ElectronicsAnalogDigitizers DT2745

16-bit @ 125 MS/s ADC
64 analog inputs, differential or single-ended, on four 2mm 40-pin header connectors
Software selectable Analog Gain up to x100
Open FPGA programming through graphical tool SCI-Compiler
Wide range of applications (from Neutrino Physics & Dark Matter to Nuclear and Particle Physics to Spectroscopic Imaging)
Suited for signals from Semiconductor Detectors coupled with CSPs (Si, HPGe) or scintillators coupled with PMTs (NaI, CsI)
On-board firmware selection for different acquisition modes:
- Scope mode (simultaneous raw waveform acquisition on common trigger)
- DPP-PHA mode (pulse height and time acquisition on independent channel self-triggers)
- DPP-PSD mode (pulse shape discrimination and time acquisition on independent channel self-triggers)
- Predisposition for other algorithms like zero suppression and data reduction
Multi-board synchronization and system building capabilities
Rack mount brackets included
Front panel fully programmable I/Os (4 LEMO TTL/NIM and 16 LVDS)
Special 125MS/s 14bit DAC output (LEMO) for signal inspection, pulse generation, majority level
2.5GB of Total Acquisition memory (DDR4)
On-board Zynq® UltraScale +™ MPSoC integrating an Arm®-based CPU running Linux®
Multi Interface: USB-3.0 and 1/10 GbE or CONET optical link (switchable on the same socket)
Fully supported by CoMPASS and WaveDump2 readout software (CoMPASS support is ^{Available on request})
SDK for embedded Arm and host PC
Open FPGA architecture for pulse analysis algorithm customization

The DT2745 Digitizer is a 64-channel digital signal processor for radiation detectors in a Desktop form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for nuclear spectroscopy using Silicon strip, segmented HPGe, Scintillation detector with PMTs, Wire Chambers, and others.

The DT2745 can perform pulse height measurements (PHA), and other algorithms that will be gradually developed, such as constant fraction timing (CFD), charge integration (QDC) and pulse shape discrimination (PSD). Algorithm settings can be set independently channel by channel.

The input channels with software selectable analog gain up to x100 are provided as differential (on 2745 versions) or single-ended (on 2745B versions).

Each channel of the module digitizes the analog input, that can be the signal coming from a physics detector, with a 16 bit, 125 MS/s ADC. The sampled data are used to initiate the digital pulse processing sequence, managed in the FPGA at the firmware level. Different firmware types can be selected via software, according to the specific setup and acquisition mode.

Common trigger: all channels acquire simultaneously with a common trigger. The trigger can be fed externally or generated by a combination of individual channel discriminators. This mode is mainly intended for the acquisition of waveforms, like a digital oscilloscope. Options for zero suppression are available to remove not significant data.
Independent trigger: suited for trigger-less applications, where no global trigger is needed but each channel acquires waveforms upon its self-trigger which fires through a digital discriminator, independently of the others.
DPP: real-time processing in the FPGA allows for the extraction of physical parameters from the waveform (e.g. pulse height, charge, timestamp, PSD), well suited for high counting rate applications. It is yet possible to save both raw waves and parameters.

A template of the firmware is available for customers who want to personalize the acquisition to implement custom algorithms for pulse processing in the open FPGA. The user can have control of the data output information and customize the trigger logic to get several combinations of self-triggers and I/O signals to validate or discard the events.
Custom software can run on the onboard CPU for data reduction and analysis. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options.
The communication interface selection offers fast readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet or optional Optical (CONET – CAEN Daisy Chainable Optical Link Protocol ^{Available on request}) Links.

Supported third-party software:

PKUCAENDAQ

Ordering Options

Code	Description
WDT2745BXAAA	DT2745B – 64 Ch. 16 bit 125 MS/s Digitizer with Programmable Input Gain, SE	RoHS
WDT2745XAAAA	DT2745 – 64 Ch. 16 bit 125 MS/s Digitizer with Programmable Input Gain, Diff	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES

GENERAL

Weight: 3120 g Form Factor: Desktop

ANALOG INPUT

Desktop Rack Dimension: Desktop: 338 W x 100 H x 283 L mm³ (without connectors)

DIGITAL CONVERSION

338 W x 100 H x 295 L mm³ (including connectors). Desktop-Rack: 19″ rack mount

SYSTEM PERFORMANCE

Channels: 64 channels, differential on 2745, single-ended on 2745B versions

Bandwidth (-3dB): 20 MHz guaranteed for all Gain settings

Impedance: differential: 100 Ω, single-ended: 50 Ω (10 kΩ personalization available)

ICMR (Input Common-Mode Range): ± 12 Vdc referred to Gnd (Differential mode only)

Full Scale Range: 4 Vpp ÷ 0.04 Vpp

Gain: x1 ÷ x100, software programmable in steps of 0.5dB independently on each 16-channel group

Connector Type: Four 2mm 40-pin header male; input adapters available

DC Offset: Adjustable in the ± 2.5V range independently on each channel

DIGITAL I/O

Resolution: 16 bits Sampling Rate: 125 MS/s simultaneously on each channel. Scalable by 2ⁿ decimation factor, n = 1 to 10 (Scope firmware only)

DAC OUT

ENOB: 12 @ 5MHz, -3dB, Gain = 1 (Typ.) RMS: 3.6 LSB (≃ 110 µV) typical RMS @ Gain = 1

ACQUISITION MEMORY

CLK-IN, CLK-OUT

Two differential pairs: o CLK, reference clock signal o SYNC, synchronization signal (start/stop, T0, etc.) 2.54mm, 4-pin AMPMODU Mod II male connector
CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
CLK-OUT: LVDS
Daisy chainable for multiboard synchronization with sw programmable CLK-OUT delay shift

LVDS I/O

16 differential pairs
Software programmable I/O (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.) – LVDS – Zdiff = 100 Ω (when set as inputs) – 2.54mm 34-pin AMPMODU Mod II male connector

TRG-IN/TRG-OUT/GPIO/S-IN – General purpose I/Os – Software programmable (trigger, gate, veto, busy, etc.) – Sigle-ended TTL/NIM

TRG-IN/S-IN internally terminated with 50 Ω (Zin = 50 Ω)
TRG-OUT requires Rt = 50 Ω
GPIO as Input must be terminated with 50 Ω
GPIO as TTL Output requires Rt = 50 Ω
GPIO as NIM Output requires Rt = 50 Ω or 25 Ω

– LEMO 00 male connector

TRIGGER

DAC output for signal inspection, pulse generation, majority level
14-bit Digital-to-Analog Converter (DAC)
125 MS/s Update Rate
±1 V @ 50 Ω load; ±2 V @ hi-Z load Output Range
LEMO-00 male connector

SYNCHRONIZATION

2.5 GB total DDR4 memory size (20.971 MS/ch) divisible in multiple buffers Maximum record length: ≃ 84 ms @ 125 MS/s (total memory size divided by 2)¹

¹Value referred to the Scope firmware (minimum of two buffers admitted)

FIRMWARE

Trigger Modes

Common: all channels acquire simultaneously with the trigger (software, external or logic combination of self-triggers)
Individual: each channel acquires independently with its self-trigger
Correlated: the individual self-trigger of each channel is validated by the coincidence/anticoincidence logic between other self-triggers and/or external I/Os

Trigger Time Stamp

Resolution: 8 ns coarse time stamp, 8ps fine time stamp (DPP firmware only)
Counter range: 48 bits
Full-scale range: ~625 h

FPGA

Clock Propagation Typical 62.5MHz frequency optionally distributed:

• By fan-out to CLK-IN

• By CLK-IN/CLK-OUT daisy chain with sw programmable CLK-OUT delay shift Custom frequencies can be supported on request

Acquisition Start/Stop Daisy chain or fan-out propagation through CLK-IN/CLK-OUT or NIM/TTL, LVDS I/Os

Data Sync Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization

Trigger Distribution TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)

Trigger Time Stamp Reset Software from START run command or Hardware from S-IN/GPIO input (Scope Firmware only)

OPEN FPGA

Firmware stored in the on-board Flash Memory and live rebootable by Web Interface

DPP Firmware Implements the digital pulse processing algorithm:

DPP-PHA: Pulse Height Analysis
DPP-QDC: Charge Integration
DPP-PSD: Pulse Shape Discrimination
DPP-ZLE: Zero Length Encoding
DPP-DAW: Dynamic Acquisition Window

Scope Firmware Firmware for the waveform recording

Upgrades Any supported firmware can be uploaded via Web Interface (both different firmware types and upgraded versions of the same firmware)

COMMUNICATION INTERFACE

Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
Programmable logic with more than 1100K system logic cells and 80Mbit memory

SOFTWARE

User-Scope Template Common trigger, simultaneous waveform recording on 64 channels management. Trigger logic and wave processing customization

User-DPP Template Individual trigger and channel acquisition management. Customization of DPP algorithm, trigger logic, and event data information

POWER REQUIREMENTS

1 GbE

Copper RJ45 or optical LC connector on SFP+ transceiver
Protocol: TCP
Transfer rate: 110 MB/s

10 GbE (Available on Request)

Copper RJ45 or LC optical connector on SFP+ transceiver
Protocol: TCP/IP, UDP
Transfer rate: 280 MB/s (TCP/IP), t. b. d. (UDP)

CONET (Available on Request)

Optical LC connector on SFP+ transceiver
CONET2 protocol (CAEN proprietary)
Transfer rate: 80 MB/s

USB 3.0

USB-C type connector
Protocol: USB 3.1 GEN1
Transfer rate: 280 MB/s

DT2745

64 Channel 16 bit 125 MS/s Digitizer with Programmable Input Gain

Software

CAEN Toolbox

COMPASS

Sci-Compiler

CAEN FELib Library

WAVEDUMP2

Firmware

D-SCOPE

D-WAVE

DPP-PSD

DPP-PHA

DPP-ZLEPLUS

DPP-SUP

Accessories

A954

A316

D-WAVE

A319A

A319B

A372F

A372M

A952

A953

Ordering Options

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