V1724

8 Input Channel 14 bit 100 MS/s Digitizer

Datasheet

Home Modular Pulse Processing ElectronicsAnalogDigitizers V1724

Digitizer Motherboard: This contains an FPGA for the read-out interface and system services.

V1724 and 724 Digitizer Family Block Diagram

Digitizer Daughterboard: This defines the digitizer type and includes the signal conditioning input stage, the ADCs, an FPGA for data processing, and the memories.

724 Digitizer Family Block Diagram

14 bit 100 MS/s ADC
FPGA for real time Digital Pulse Processing:
8 input channels (single-ended)
2.25 Vpp input range (default); 10 Vpp and 0.5 Vpp customization by ordering option
16-bit programmable DC offset adjustment in the full range independently on each channel
Sampling rate decimation factor
Trigger Time stamps
Multi-Event Memory buffer: 512 kS/ch or 4 MS/ch, divisible into up to 1024 buffers
Programmable event size and pre-post trigger adjustment
Signal Inspection/Analog Sum/Majority and digital over/under threshold flags for Global Trigger logic
Front panel clock input/output available for multiboard synchronization (direct feed through or PLL-based synthesis)
16 programmable LVDS I/Os
Optical Link interface (CONET proprietary protocol) Daisy-chainable through A5818 (PCIe Gen 3) Controller or A4818 (USB3-to-CONET)
VME64X compliant interface
Firmware upgradeable via VME/Optical Link
Fully supported by CoMPASS and WaveDump2 software

The CAEN Mod. V1724 is a Waveform Digitizer, in VME64 form factor, housing 8 Input Channel 14 bit 100 MS/s Flash ADC, designed for waveform recording and supporting advanced algorithms for online digital pulse processing (DPP).

The Digitizer is well suited for high-resolution detectors as Silicon, HPGe or inorganic scintillators like NaI or CsI coupled with Charge Sensitive Preamplifiers. In the waveform recording mode, algorithms of zero suppression are also implemented to reduce the data throughput. The acquisition can be channel independent and it is possible to make coincidence/anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems.

In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improve the throughput performances. Piled-up events can be rejected or saved for offline analysis. The acquisition in DPP-PHA mode is fully controlled by the CoMPASS software, which manages the algorithm parameters, build the plots and saves the relevant energy and time spectra. In the case of waveform recording mode, the user can take advantage of the WaveDump or WaveDump2 software to access and save the waveforms. For DPP-DAW mode, a C demo fully controls the acquisition, data plotting and saving.

Libraries and demo software in C, Phyton, and LabView are available for integration and customization of specific acquisition systems.
The communication to and from the board is provided through the VMEBus and Optical Link interfaces.

Note: V1724 can be operated with VME8004B / VME8004X / VME8008B / VME8008X /NV8020A/VME8010 / VME8011 / VME8100 / VME8200/μ-crate.

Never use this digitizer with crates VME8001, VME8002, VME8004, and VME8004A. Overheat may damage the module.

Ordering Options

Code	Description
WV1724BXAAAA	V1724B – 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE (Obsolete)
WV1724CXAAAA	V1724C – 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C4, DIFF (Obsolete)
WV1724DXAAAA	V1724D – 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, DIFF (Obsolete)
WV1724EXAAAA	V1724E – 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE	RoHS
WV1724FXAAAA	V1724F – 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, DIFF (Obsolete)
WV1724GXAAAA	V1724G – 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C20, SE	RoHS
WV1724XAAAAA	V1724 – 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C4, SE (Obsolete)

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO

GENERAL

Weight: 535 g
Form Factor: 1-unit wide VME64
Dimension: 6U x 160 mm

ANALOG INPUT

Number of Inputs: 8, single-ended, DC coupled
Bandwidth (-3dB): 40 MHz
Impedance: 50 Ω
Gain: x1, fixed
Connector Type: MCX
Full Scale Range: 2.25 Vpp default; 10 Vpp and 0.5 Vpp customization by ordering option
16-bit programmable DC offset adjustment in the full range independently on each channel
Abs. Max. Voltage Rating: 6 Vpp @2.25Vpp (with Vrail max +6 V or –6 V) for any DAC offset value

DIGITAL CONVERSION

Resolution: 14 bits
Sampling Rate:
- 100 MS/s simultaneously on each channel (nominal)
- Down to 16.1 MS/s by hardware downsampling* (AN6308)
- Down to 781 kS/s by decimation function (Waveform Recording firmware only)

*The minimum value may depend on the digitizer model, the firmware, and the hardware downsampling mode.

SYSTEM PERFORMANCES

ENOB: 11.89 (64 kS Buffer)
SINAD: 73.85 dB
THD: 87.8 dB
SFDR: 93.5 dB
SIGMA: 1.09 LSB rms (64 kS buffer, open input)

DIGITAL I/O

LVDS I/O	TRG-IN/TRG-OUT/S-IN
16 differential pairs Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.) LVDS Zdiff = 100 Ω (when set as inputs) 2.54mm 34-pin AMPMODU Mod II male connector	General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, veto, busy, etc.) TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω) TRG-OUT requires Rt = 50 Ω

ANALOG OUT

Software programmable DAC output (12-bit/100MHz) with five operating modes:
- Test Waveform: 1 Vpp test ramp generator
- Majority signal: proportional to the number of channels (enabled) under/over threshold (1 step = 125 mV)
- Inspection signal: proportional to the sum of the board channels
- Buffer Occupancy: output signal is proportional to the Multi Event Buffer Occupancy (1 buffer ~ 1 mV)
- Voltage level: output signal is a programmable voltage level (0 to +1 V range with 12-bit resolution)

ACQUISITION MEMORY

512 kS/ch (5 ms @ 100 MS/s) or 4 MS/ch (40 ms @ 100 MS/s) Multi Event Buffer divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre/post-trigger

COMMUNICATION INTERFACE

VMEbus	Optical Link
VME64X compliant Data modes: D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast Cycles Transfer Rate: 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST) Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access	CAEN proprietary CONET protocol Transfer Rate: up to 80 MB/s Daisy Capability: up to 8 ADC modules per single optical link by A5818 Controller or A4818 Adapter

TRIGGER AND EVENT ACQUISITION

Triggered Mode

Trigger Sources

Trigger Timestamp – Waveform Rec. firmware

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals; a zero suppression function is available.

Software by register writing
External upon the leading edge of The TRG-IN signal (TTL/NIM)
Local (self-trigger) upon the channel discriminator with programmable threshold

Resolution: 20 ns
Counter range: 31 bits (default); extendable to 48-bit by firmware
Full-scale range: ~ 21 s @31-bit

Streaming Readout Mode

Each channel autonomously identifies the ROI and uses the local trigger to get events independently on the other channels; validation logics can be configured for correlated acquisition (coincidence/anticoincidence).

Trigger Timestamp – DPP firmware

DPP-PHA:

Resolution: 10 ns
Counter Range: 30 bits (default); extendable to 46-bit by firmware, to 64-bit by software
Full-scale range: ~ 10 s @30-bit

DPP-DAW:

Resolution: 10 ns
Counter Range: 31-bit (default); extendable to 64-bit by software
Full-scale range: ~ 21 s @31-bit

SYNCHRONIZATION

Clock Generation

CLK-IN/CLK-OUT Connector

By default, the Digitizer’s main clocks are generated upon a 50MHz reference frequency that can optionally be internal (50MHz local Oscillator) or external (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

Reference clock differential signal
2.54mm 3-pin AMPMODU Mod II male connector
CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
CLK-OUT: LVDS

Clock Synchronization

Default 50MHz frequency distributed by:

Fan-in into CLK-IN (DT4700)
CLK-IN/CLK-OUT Daisy chain with sw programmable CLK-OUT delay shift

PLL programming files for supported custom frequencies can be generated and loaded by the CAEN Toolbox software.

Data Synchronization

Programmable Busy/Veto logic on differential LVDS I/O, or single-ended NIM/TTL I/O for event building.

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-in propagation through differential LVDS I/O or single-ended NIM/TTL I/O.

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/O (global trigger) or LVDS I/O (global or local trigger).

FPGA

Altera Cyclone EP1C20
One FPGA serves 1 channel

CAEN FIRMWARE

DPP Firmware (Shareware)

Waveform Recording Firmware (Freeware)

Upgrades (Free)

Pay firmware implementing a digital pulse processing algorithm:

DPP-PHA: Pulse Height Analysis
DPP-DAW: Dynamic Acquisition Window

30-minute per power cycle in Trial mode; license is required for full-time work.

Designed for waveform recording.

Web available CFA files for Waveform Recording and DPP firmware upgrade through the CAEN Toolbox software, via VMEbus or Optical Link.

SOFTWARE

Readout Software for Waveform Rec. Firmware (Freeware)	Readout Software for DPP Firmware (Freeware)	SDK and Tools (Freeware)
CAEN WaveDump: Digitizer 1.0 series support, single-board management, user-customizable WaveDump2: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based	CoMPASS: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based DPP-DAW Readout Demo: sample code with C source files to dial with the DAW functionalities and help in user’s DAQ development	General-purpose libraries (C/Python, LabVIEW) with demo samples for host Windows® and Linux® PC.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER CONSUMPTIONS

+5 V: 4.5 A (Typ.)
+12 V: 0.2 A (Typ.)
-12V: 0.2 A (Typ.)

V1724

8 Input Channel 14 bit 100 MS/s Digitizer

Software

CAEN Toolbox

CAENDigitizer Library

COMPASS

WaveDump

CAEN FELib Library

WAVEDUMP2

Firmware

D-WAVE

DPP-PHA

DPP-DAW

DPP-SUP

Accessories

A4818

A954

Digitizers Input Range Personalizations

A316

A318

DT4700

A317

A5818

A319B

AI2700

A654

A659

A952

A953

Ordering Options

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