DT5203

Dimensions: 106.1 W x 56.1 H x 186.8 L mm³ (including A5255 pins)

Weight: 503 g

64 channels (four 17 x 2, 2.54 mm pin header pins)

Removable panel to expose 1 edge connector type HSEC8-170 – Mating connector: Samtec HSEC8-170-01-S-DV

Input Type: LVDS

• Input voltage: Min = -40 mV  Max = +1500 mV

• Common Mode: Min = +70 mV  Max = +1200 mV

• Differential voltage: Min = +140 mV Max = +450 mV

• Input Termination: 100 Ω

LSB = 3.125 ps

• ΔT_RMS = ∼5 ps. Tested with LVDS signals, two passive splitters and delay cables

• ΔT_RMS = ∼7 ps. Tested with pulse generator (1 Vpp, 0.8 ns rise/fall), passive splitter and 5 ns cable delay

• ΔT_RMS = ∼20 ps with variable amplitude pulses (30 mV to 1 V) and walk correction by ToT

Time measurement dynamic range in picoTDC:

• Leading Edge only: T_LEAD = 24 bits (FSR = ∼ 52 μs)*

• Leading + Trailing Edge: T_LEAD / T_TRAIL = 24 bits (FSR = ∼ 52 μs)*

• Leading + ToT8: T_LEAD = 19 bits, T_TOT = 8 bits (LSB size and FSR can be programmed)

• Leading + ToT11: T_LEAD = 16 bits, T_TOT = 11 bits (LSB size and FSR can be programmed)

Coarse time stamp in FPGA (56 bits @ 12.6 ns) con be combined with picoTDC data to extend the full scale range of the time measurement to a maximum dynamic of 64 bit (streaming acquisition mode).

^{* 26 bits (FSR = ∼ 210 μs) optional}

Common Start: TDC ch. 0 is the common start that opens the acquisition gate and represents the time reference. All other channels provide ΔT time measurements: T_LEAD = ΔT_N = T_N – T₀. The gate width is programmable by software. Any hit falling outside the gate will be discarded.

Output Data: T_LEAD  or  T_{LEAD +} ToT

Common Stop: Same as common start, but ch. 0 is used as a common stop that closes the acquisition gate: ΔT_N = T₀ – T_N.

Output Data: T_LEAD  or  T_{LEAD +} ToT

Trigger Matching: The trigger signal (typ. from T0/T1 inputs) defines an acquisition window with programmable width and offset. All hits falling into the window will be recorded. Multi-hit acquisition is supported. All time measurements are referred to the Coarse Trigger Time Stamp (LSB = 25.6 ns), while the relative time between the hits keeps the maximum timing resolution (LSB = 3.125 ps).

Output Data: T_LEAD or T_LEAD+T_TRAIL or T_LEAD+ToT

Streaming: Continuous hit recording, without any gate or trigger windowing. All hit time measurements are expressed as 64 bit time stamps (LSB = 3.125 ps) and saved in the form of a sorted list.

Output Data: T_LEAD or T_LEAD+T_TRAIL (or T_LEAD+ToT , COMING SOON)  

• 56-bit counter, 25.6 ns step

• up to 128 boards can be synchronized with the DT5215 FERS-CB by sending a time stamp reset signal via TDlink

• T0-IN, T1-IN: LEMO-00 connector, NIM or TTL (terminated to 50 Ω)

• T0-OUT, T1-OUT: LEMO-00 connector, TTL (50 Ω termination required)

Jumpers for IN-OUT bypass and termination removal (daisy chaining).

Functions (SW programmable): Trigger, Acquisition Start/Stop, Sync, Busy, Veto, Signal inspection, etc…

T0/T1 inputs can be used to drive TDC-Ch0 = Tref (possible degradation of the resolution because of the FPGA temperature dependence)

• GREEN: Power-ON, Init-Done, Run, Trigger, Data Ready, T0-IN, T1-IN

• ORANGE: Event Overrun (rejected triggers because received while busy)

• RED: Failure (missing clock, over-temperature, etc…)

Fast LVDS output (one signal only) with programmable frequency and width, for debug purposes

• Firmware of FPGA upgrade via USB, Ethernet, or TDlink 

• Firmware of µC upgrade via Ethernet only

Readout SW

Fully controlled by the Janus 5203 open source software for Windows® and Linux®. It can run in console mode (C program, with console commands and gnuplot display for plots) or connected to a GUI (Python) that implements user friendly configuration panels and run controls. Janus 5203 can acquire, plot and save output files with ToA, ToT histograms, as well as list files (trigger timestamp, ToA and ToT for each channel).

Web Interface Board information and monitoring, Ethernet configuration.

• Environmental: Indoor use

• Operating Temperature: 0 °C to +40 °C

• Storage Temperature: -10 °C to +60 °C

• Operating Humidity: 10% to 90% RH non condensing

• Storage Humidity: 5% to 90% RH non condensing

• Altitude:< 2000m

• Pollution Degree: 2

• Overvoltage Category: II

• EMC Environment: Commercial and light industrial

• IP Degree: IPX0 Enclosure, not for wet location

EMC: CE 2014/30/EU Electromagnetic compatibility Directive

SAFETY: CE 2014/35/EU Low Voltage Directive

Single power supply: +12 V. Accepted voltage range: MIN +7 V, MAX +15 V

(110 V/220 V AC/DC converter provided with Desktop version only)

700 mA @ +12 V, i.e ∼ 8.4 W