DT5204

Dimensions: 106.1 W x 56.1 H x 220.8 L mm³ (including A5250 pins)

Weight: 535 g

64 channels

Input edge connector type Samtec HSEC8-170

Mating connector: Samtec HSEC8-170-01-S-DV

Signal polarity: Positive

Each SiPM input has two pins:

• Cathode with HV bias (min = +20 V, max = +80 V)

• Anode closed to ~100 ohm, feeding the Radioroc inputs

HV module for SiPM biasing (A7585D)

HV Range: +20 V/+80 V, Max 10 mA

Individual bias adjustment on channel basis (8 bit DACs, LSB = ~2 mV, adjust range = 550 mV)

Automatic temperature feedback for SiPM gain stabilization

Spectroscopy:

The common trigger initiates the peak sensing detection and A/D conversion (12 bit) on all channels simultaneously. Conversion time = ~10 μs. Output Data: Trigger time stamp, Trigger ID, PHA (Low and/or High Gain). Zero suppression with programmable threshold.

Counting:

32 bit counters, up to 200 MHz. Common trigger defines dwell time (i.e. counting window). No dead-time between subsequent windows. Internal period trigger from 16 ns to ~34 s. Output Data: Trigger time stamp, Trigger ID, channel counts. Zero suppression available. Counters are automatically reset after each trigger.

Timing (Common Start):

The Tref signal (T0, T1 inputs) is a common start that opens the acquisition gate with programmable width. Channel self-triggers are acquired as ΔT from Tref and, optionally, as ToT for PHA estimation. Output Data: Trigger (=Tref) time stamp, Trigger ID, ΔT or ΔT+ToT

Timing (Common Stop):

Same as common start, with Tref used as a common stop that closes the acquisition gate. Acquired events are those ones arrived before the trigger (look back acquisition).

Timing (Trigger Matching):

The common trigger signal defines an acquisition window with programmable width and offset. All hits falling into the window will be recorded. Multi-hit acquisition is supported. Output Data: Trigger time stamp, Trigger ID, ToA or ToA+ToT

Timing (Streaming):

Continuous hit recording, without any gate or trigger windowing. All hit time measurements are expressed as 64 bit time stamps and saved in the form of a sorted list. Output Data: ToA or ToA+ToT

• High Gain: Min = 5, Max = 80, 16 steps (1 step = 5)

• Low Gain: Min = 0.5, Max = 8, 16 steps (1 step = 0.5)

• Short Range: Min = 20 ns, Max = 300 ns, 16 steps (1 step = 20 ns)

• Long Range: Min = 80 ns, Max = 1200 ns, 16 steps (1 step = 80 ns)

Up to 2000 photo-electrons @ 10⁶ SiPM gain

Dedicated fast preamps + discriminator for SiPM pulse detection. Trigger down to 1/3 p.e.

Fast Preamp Gain: Min = 15 (BW = 480 MHz), Max = 100 (BW = 55 MHz), 32 steps

Discriminator Dual Threshold: Range = 278 mV; 1024 steps, 1 step = 0.27 mV

55 ps FWHM on a single p.e.

Time Stamp Range: 64 bit

Intrinsic timing resolution of picoTDC = 3.125 ps LSB

Time over Threshold (ToT): 1% linearity energy measurement up to 2000 p.e.

Photon counting up to 200 Mcps per channel

MCS mode with programmable dwell time: from 16 ns to ~34 s

Global trigger common to 64 channels: used in Spectroscopy mode to start Peak acquisition, in Timing mode to generate the acquisition windows (Gate). Trigger-less acquisition only in Streaming mode.

Global Trigger Sources:

• OR of self-triggers = OR(0..63)

• Plane coincidence: OR(0..31) AND OR(32..63)

• Paired channels: AND(0..1) OR AND(2..3) … OR AND(62..63)

• Majority with programmable threshold

• External trigger (T0-IN, T1-IN, LEMO, TTL/NIM)

• Internal periodic trigger with programmable frequency

Acquisition Trigger Time Stamp: 56 bit, step = 8 ns

Two synchronization modes:

• T0 or T1 IN-OUT daisy chain: max jitter = 100 ns

• fiber optic (TDlink) and DT5215 Concentrator: up to 128 boards, max jitter 50 ps

T0-IN, T1-IN: LEMO-00 connector, NIM or TTL (terminated to 50 Ω)

T0-OUT, T1-OUT: LEMO-00 connector, TTL (50 Ω termination required)

SW selectable IN-OUT bypass and termination removal for daisy chaining

Functions (SW programmable):

Trigger, Acquisition Start/Stop, Sync, Busy, Veto, Signal inspection, etc…

SMA connectors allowing the user to acquire analog signals from a specific, software selectable stage of each Radioroc signal shaping chain:

• LG/HG Preamplifier output

• LG/HG Slow Shaper output

• Fast Shaper output

• GREEN: Power-ON, Init-Done, Run, Trigger, Data Ready, T0-IN, T1-IN

• ORANGE: Event Overrun (rejected triggers because received while busy)

• RED: Failure (missing clock, over-temperature, etc…)

Radioroc provides a test input pin that can be internally connected to the pre-amplifier inputs, channel by channel. The test signal can come from an external signal (MCX connector on the PCB) or generated by an internal pulser with programmable amplitude. The internal pulser can be trigger by T0/T1 IN or by the internal periodic trigger.

• Firmware of FPGA be upgraded via USB, Ethernet or Optical Link

• Firmware of μC can be upgraded via Ethernet only

Readout SW
Fully controlled by the Janus 5204 open source software for Windows® and Linux®.
It can run in console mode (C program, with console commands and gnuplot display for plots) or connected to a GUI (Python) that implements user friendly configuration panels and run controls.

Janus 5204 can perform multiple board acquisition of  PHA energy spectrum (Low and High Gain). ToT spectrum (represents PHA in timing mode) DT spectrum, with event building based on trigger ID or time stamp.

Live Display: channel hit count and rate, trigger rate, lost triggers, data throughput, acq. time, etc… Plots: PHA, DT, ToT, hit rate, 2-D heat map with channel hit rates or PHA.

Output Files: histograms (spectra), list files (PHA, ToA, ToT, ΔT), Run Info, Sync file.

Web Interface
Board information and monitoring, Ethernet configuration.

Single power supply (+12 V). Regularly working in a range between +7 V and +15 V.

110/220V AC/DC converter provided with Desktop version only.