V1782

• Form Factor: 2-unit wide VME 6U module

• Weight: 800 g

• Operational Conditions: 0 to 50°C Temperature Range

• Compliance: EMC compliant

Number of Inputs: 8

Input Features:

• BNC connector

• Single ended, DC and 10 μs AC coupling hardware selectable

• Impedance: 1 kΩ

• Positive and negative signals accepted

• Analog Coarse Gain: x1, x2, x4, x8 software selectable (Gain 1 = 1 Vpp); gain attenuation x0.2 by on-board jumper

• Programmable DC offset adjustment on each input in the full-scale range

• Resolution: 16 bits

• Sampling Rate: 100 MS/s (simultaneously on each input)

• Trapezoidal filter for the energy calculation: adjustable rise time 0.02 to 40 μs; flat top 0.02 to 40 μs
• Trigger and Timing filter based on integrative-derivative component (30-bit time stamp, 10 ns resolution, 10 s range, 64-bit extension by software, roll-over tracking event)
• Trigger threshold adjustment
• Digital fine gain: 1 to 2.2 in steps of 0.0001
• Trapezoid tail correction; decay time 0.1 to 650 μs
• Trigger time tag discrimination by RC-CR2 filter; shaping time 0.01 to 2.4 μs
• Trigger hold-off (imposed dead-time) to prevent after pulses: 0 to 40 μs
• Programmable Pile-up Guard duration: 0 to 80 μs beyond the end of the flat top
• Baseline restorer: fast, medium, slow

• Pulse Height Analysis (PHA): 1k-2k-4k-8k-16k-32k pulse height histogram built at software level
• List mode: pulse height and time stamp for each event
• Oscilloscope mode: signal inspection of input pulses and internal filters outputs

• Uncorrelated: each channel operates independently (based on channel self-trigger)
• Correlated: coincidence/anticoincidence among channels and/or an external trigger (TRG-IN)
• External: channels are triggered by external trigger only (TRG-IN)

• CLK-IN (3-pin AMPMODU II): AC-coupled differential clock input LVDS, ECL, PECL, LVPECL, CML (single-ended NIM/TTL adaptor orderable); Jitter < 100ppm requested

• CLK-OUT (3-pin AMPMODU II): AC-coupled differential clock output

• TRG-IN (LEMO): General purpose single-ended digital input Software programmable functions NIM/TTL, Zin = 50 Ω

• TRG-OUT (LEMO): General Purpose Digital output Software programmable functions NIM/ TTL, Zin = 50 Ω

• S-IN (LEMO): TTTReset/AcqStartStop digital Input NIM/TTL, Zin = 50 Ω

• LVDS I/O (32-pin AMPMODU II): 16 general purpose differential LVDS I/O; An input pattern from the LVDS I/O can be associated to each trigger as an event marker Multiple functions configurable by register

• 12-bit / 100MHz DAC FPGA controlled

• 1 Vpp dynamics, 50 Ω termination

• Configurable for test signals

• Optical Link
  CAEN CONET proprietary protocol, Up to 80 MB/s transfer rate; Daisy chain capability by connecting up to 8 or 32 ADC modules to a single Optical Link Controller (A4818 or A5818 respectively)

• VME
  VME 64X compliant interface, Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge) CBLT32/64, 2eVME, 2eSST (up to 200 MB/s)

• DPP-PHA firmware can be upgraded via VMEbus/Optical Link

• Fully controlled by CoMPASS spectroscopy software (up to 32k PHA histogram supported).

• General purpose C libraries with demo samples available for developers Windows® and Linux® OS supported

• 5.6 A @ +5V;

• 0.320 A @ +12 V;

• 0.180 A @ -12V