DT5202

FERS-5200 is a front‐end readout system designed for the readout of large detector arrays, such as SiPMs, multi‐anode PMTs, Silicon Strip detectors, Wire Chambers, GEMs, Gas Tubes and others. FERS‐5200 is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels with preamplifier, shaper, discriminator, ADC, trigger logic, synchronization, local memory and readout interface. In most cases, the front‐end is based on ASIC chips that allow for high density, cost effective integration of multi‐channel readout electronics into small size and low power modules.

The first FERS‐5200 unit being developed is the A5202 (DT5202 is the boxed version for desktop use) that uses the Citiroc‐1A chip produced by WeeROC for SiPM readout. More precisely, the DT5202 houses two Citiroc‐1A chips (64 readout channels). Each readout channel is composed of a Preamplifier, a Slow Shaper with peak sensing detector and a Fast Shaper followed by a discriminator. Peak sensing values from each Citiroc‐1A are converted sequentially (multiplexed output) by an ADC. The 64 channel self‐triggers (discriminator outputs) can be used for counting, time stamping, to determine the Time over Threshold (ToT) information and also to generate the board bunch trigger that starts the A/D conversion. The DT5202 board is also provided with the A7585D power supply module for biasing the SiPMs and the interfaces for readout, synchronization and control.

The most relevant DT5202 acquisition modes are:

• Spectroscopy Mode: This mode (also indicated as Pulse Height Analysis, PHA) works with a global (bunch) trigger, either coming from an external source or generated by a combination of the channel self‐triggers. As soon as a trigger is issued, all channels start simultaneously the A/D conversion of the pulse amplitude.

• Counting Mode: In this mode, the self‐triggers of each channel are individually counted, with the counting intervals defined by an internal periodic gate with programmable width or by an external signal.

• Timing Mode: This mode generates a list of individual time stamps (referred to a Time Reference signal) optionally combined with the Time over Threshold (ToT) information that gives a rough estimation of the pulse amplitude. 

One DT5202 unit can be used stand alone, without any additional hardware, just connected to the PC via USB 2.0 or Ethernet 10/100T.

For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink that allows up to 16 FERS‐5200 units to be connected in daisy chain (ring) providing data readout, synchronization between the units and broadcasting of commands (e.g. start/stop run, time resets, etc.). The DT5215 is a data collector board (FERS‐CB) housing 8 TDlink masters that will make it possible to manage up to 128 FERS‐5200 units.

The DT5202 is fully supported by the CAEN Janus 5202 Open Source software on Windows^® and Linux^®.  Janus can run in console mode (C program, without graphics) or connected to a GUI written in Python. The GUI has configuration and run control panels that simplify the data acquisition management. Both console and GUI modes permits to acquire data from multiple boards, manage the event building and timing histograms, display data statistics, plot histograms, and save output, including spectra and list files with the acquired timing data.

The DT5202 is supplied as standard with the A5250 adapter pre-installed on the rear panel, ensuring a ready-to-use default configuration. If a different compatible adapter is required, it must be ordered separately as an additional item.

A wide range of alternative compatible adapters is available to meet different application needs. View the full list here.