VX1724

• 16 differential pairs

• Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)

• LVDS

• Zdiff = 100 Ω (when set as inputs)

• 2.54mm 34-pin AMPMODU Mod II male connector

• General-purpose digital I/Os

• Sigle-ended TTL/NIM

• LEMO 00 male connector

• Software programmable function (trigger, veto, busy, etc.)

• TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω)

• TRG-OUT requires Rt = 50 Ω

• VME64X

• Data modes: D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast Cycles

• Transfer Rate: 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST)

• Sequential and random access to the data of the Multi Event Buffer

• The Chained readout allows to read one event from all the boards in a VME crate with a BLT access

• CAEN proprietary CONET protocol

• Transfer Rate: up to 80 MB/s

• Daisy Capability: up to 8 ADC modules per single optical link by A5818 Controller or A4818 Adapter

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals; a zero suppression function is available.

• Software by register writing

• External upon the leading edge of The TRG-IN signal (TTL/NIM)

• Local (self-trigger) upon the channel discriminator with programmable threshold

• Resolution: 20 ns

• Counter range: 31 bits (default); extendable to 48-bit by firmware

• Full-scale range: ~ 21 s @31-bit

Streaming Readout Mode

Each channel autonomously identifies the ROI and uses the local trigger to get events independently on the other channels; validation logics can be configured for correlated acquisition (coincidence/anticoincidence).

Trigger Timestamp – DPP firmware

DPP-PHA:

• Resolution: 10 ns

• Counter Range: 30 bits (default); extendable to 46-bit by firmware, to 64-bit by software

• Full-scale range: ~ 10 s @30-bit

DPP-DAW:

• Resolution: 10 ns

• Counter Range: 31-bit (default); extendable to 64-bit by software

• Full-scale range: ~ 21 s @31-bit

By default, the Digitizer’s main clocks are generated upon a 50MHz reference frequency that can optionally be internal (50MHz local Oscillator) or external (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

• Reference clock differential signal

• 2.54mm 3-pin AMPMODU Mod II male connector

• CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)

• CLK-OUT: LVDS

Clock Synchronization

Default 50MHz frequency distributed by:

• Fan-in into CLK-IN (DT4700)

• CLK-IN/CLK-OUT Daisy chain with sw programmable CLK-OUT delay shift

PLL programming files for supported custom frequencies can be generated and loaded by the CAEN Toolbox software.

Data Synchronization

Programmable Busy/Veto logic on differential LVDS I/O, or single-ended NIM/TTL I/O for event building.

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-in propagation through differential LVDS I/O or single-ended NIM/TTL I/O.

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/O (global trigger) or LVDS I/O (global or local trigger).

Pay firmware implementing a digital pulse processing algorithm:

• DPP-PHA: Pulse Height Analysis

• DPP-DAW: Dynamic Acquisition Window

30-minute per power cycle in Trial mode; license is required for full-time work.

Designed for waveform recording.

Web available CFA files for Waveform Recording and DPP firmware upgrade through the CAEN Toolbox software, via VMEbus or Optical Link.

• CAEN WaveDump: Digitizer 1.0 series support, single-board management, user-customizable

• WaveDump2: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based

• CoMPASS: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based

• DPP-DAW Readout Demo: sample code with C source files to dial with the DAW functionalities and help in user’s DAQ development

General-purpose libraries (C/Python, LabVIEW) with demo samples for host Windows® and Linux® PC.