Obsolete

N6720

4 Channel 12 bit 250 MS/s Digitizer

Home Modular Pulse Processing ElectronicsAnalogDigitizers N6720

12 bit 250 MS/s ADC
FPGA for real time Digital Pulse Processing:
- Pulse Shape Discrimination (DPP-PSD)
- Zero Suppression (Waveform Recoding Firmware)
4/2 channels
MCX input (50 Ω, single ended)
2 Vpp single ended input range
16-bit programmable DC offset adjustment: ±1 V
Trigger Time stamps
Memory buffer: 1.25 MS/ch or 10 MS/ch
Programmable event size and pre-post trigger adjustment
Optical Link interface (CAEN proprietary protocol)
USB 2.0 interface
Firmware upgradeable via USB/Optical Link
Libraries, Demos (C and LabView) and Software tools for Windows and Linux

The CAEN Mod.N6720 is a 4/2 Channel 12-bit 250 MS/s NIM Waveform Digitizer with 2 Vpp single ended input dynamics on MCX coaxial connectors. The DC offset is adjustable via a 16-bit DAC on each channel in the ±1V range.
The model is available in 4 versions: with 2 or 4 channels, different Multi event Buffer memory and different FPGA densities:

Version	N6720B	N6720D	N6720C	N6720E
No of Channels	4	4	2	2
Cyclone FPGA	EP1C20 (20.000 LEs)	EP1C20 (20.000 LEs)	EP1C20 (20.000 LEs)	EP1C20 (20.000 LEs)
Memory	1.25MS/ch	10MS/ch	1.25MS/ch	10MS/ch

The module features a front panel Clock Input and a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read by USB or Optical Link. The acquisition can continue without dead time in a new buffer.

Each channel has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of programmable size. Two sizes of the channel digital memory are available by ordering options: 1.25 MS/ch and 10 MS/ch. The readout (by USB or Optical Link) of a frozen buffer is independent from the write operations in the active circular buffer (ADC data storage). ‘Zero suppression’ and ‘data reduction’ algorithms allow substantial savings in data amount readout and processing, rejecting samples smaller than programmable thresholds. N6720 supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple N6720 boards.

The trigger signal can be provided externally via the front panel Trigger Input as well as via the software, but it can also be generated internally thanks to threshold self-trigger capability.

N6720 houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A2818).

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

CAENSCOPE: fully graphical program that implements a simple oscilloscope.
CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.

Digital Pulse Processing firmware for Physics Applications – this special firmware allows to perform on-line processing on detector signal directly digitized:

DPP-PSD Digital Pulse Processing for Pulse Shape Discrimination
x720(*) and x751 digitizers running DPP-PSD firmware accept signals directly from the detector and implement a digital replacement of dual gate QDC, discriminator and gate generator.

(*) DPP-CI firmware and DPP-CI Control Software are no longer supported. To perform Charge Integration please refer to the DPP-PSD firmware and software

Ordering Options

Code	Description
WN6720BXAAAA	N6720B – 4 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE (Obsolete)	RoHS
WN6720CXAAAA	N6720C – 2 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE (Obsolete)	RoHS
WN6720DXAAAA	N6720D – 4 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C20, SE (Obsolete)	RoHS
WN6720EXAAAA	N6720E – 2 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C20, SE (Obsolete)	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO


GENERAL	1-unit wide NIM module
ANALOG INPUT	4/2 channels (MCX 50 Ω) Single-ended Input range: 2 Vpp Bandwidth: 125 MHz Programmable DAC for Offset Adjustment x channel: ±1 V
DIGITAL CONVERSION	Resolution: 12 bit Sampling rate: 31.25 to 250 MS/s simultaneously on each channel
SYSTEM PERFORMANCE	ENOB: 10.14 (64 kS Buffer) SINAD: 62.85 dB THD: 74.1 dB SFDR: 82.0 dB SIGMA: 0.95 LSB rms (64 kS Buffer, open input)
ADC Sampling Clock generation	Three operating modes: PLL mode: internal reference (50 MHz loc. oscillator) PLL mode: external reference on CLK_IN PLL Bypass mode: ext. clock on CLK_IN drives directly ADC clocks (Freq.: 31.25 ÷ 250 MHz)
DIGITAL I/O	CLK_IN (AMP Modu II): AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML(single ended NIM/TTL available by custom cable) Jitter <100 ppm TRG_IN (LEMO 50 Ω, NIM/TTL): external trigger input GPI/GPO (LEMO 50 Ω, NIM/TTL): programmable front panel input/output
ACQUISITION MEMORY	1.25 MS/ch (5 ms @ 250 MS/s) or 10 MS/ch (40 ms @ 250 MS/s) Multi Event Buffer divisible into 1 ÷ 1024 buffers Independent read and write access Programmable event size and pre/post-trigger
TRIGGER	Common Trigger External (signal on TRG_IN) Software (by USB or Optical Link) Self trigger (internal threshold self-trigger)
TRIGGER Time Stamp	31-bit counter – 16 ns resolution – 17 s range
MULTI MODULES SYNCHRONIZATION	Clock distribution: by Fan Out Trigger distribution: by Daisy chain or Fan Out Time stamp synchronization
ADC AND MEMORY CONTROLLER FPGA	One Altera Cyclone EP1C4 or EP1C20 per channel
USB INTERFACE	USB2.0 compliant Up to 30 MB/s transfer rate
OPTICAL LINK	CAEN proprietary protocol, up to 80 MB/s transfer rate Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A2818/A3818)
UPGRADE	Firmware can be upgraded via Optical Link or USB interface
SOFTWARE	General purpose C and LabView Libraries Demo and Software Tools for Windows and Linux
POWER CONSUMPTION	2.9 A @ +6 V 90 mA @ -6 V

N6720

4 Channel 12 bit 250 MS/s Digitizer

Software

CAEN Toolbox

CAENDigitizer Library

Firmware

D-WAVE

DPP-PSD

Accessories

A318

DT4700

A317

A3818

AI2700

A654

A659

Ordering Options

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