DT2740

64 Input Channel 16 bit 125 MS/s Digitizer

Datasheet

Home Modular Pulse Processing ElectronicsAnalogDigitizers DT2740

Rack mount brackets included

64 independent input channels, 125 MS/s 16-bit, with individual DC offset adjustment
Front panel readout via USB-3.0 or 1Gb Ethernet
On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
2.5GB of total acquisition memory (DDR4)
Open FPGA architecture fully supported by SCI-Compiler tool
Ready-to-Use Firmware solutions to get time-stamped waveforms and physical quantities (check here for the available options)
Triggered and Streaming Readout modes supported
System features: Multi-board synchronization, digital I/Os for trigger logic, on-board storage of multiple firmware images, 125MS/s 14-bit DAC output and integrated web interface
Software ecosystem:
- GUI-based readout software available for multiparametric spectroscopy (CoMPASS) or waveform recording (WaveDump2)
- Firmware/software generator and compiler for the Open FPGA (Sci-Compiler), eliminating the need for FPGA programming skills
- Libraries (FELib) and demo codes are provided for software customization
Wide range of applications (from Neutrino Physics & Dark Matter to Nuclear and Particle Physics to Spectroscopic Imaging)
Suited for signals from Semiconductor Detectors coupled with CSPs (Si, HPGe) or scintillators coupled with PMTs (NaI, CsI)

The CAEN mod. DT2740 Digitizer is a 64 input channel digital signal processor for radiation detectors in the Desktop form factor. It not only offers waveform digitization and recording, but also Multi-Channel Analysis for nuclear spectroscopy using Silicon strip, segmented HPGe, Scintillation detector with PMTs, Wire Chambers, and others.

Each input channel is able to independently digitizing detector signals through a 16-bit ADC at 1 GS/s. Data acquisition is driven by trigger signal generation and the identification of a Region of Interest (ROI), defined in terms of sample count or time duration. Trigger sources can be local (channel self-trigger), external, or software-based. Once acquired, the digitized data is processed within the FPGA, stored in high-speed memory as events—including Trigger ID and Timestamp tags—and then transferred via high-bandwidth communication interfaces for further analysis.

The digitizer supports different acquisition modes, designed to balance throughput, latency, and data efficiency according to experimental requirements:

Triggered Mode: All channels acquire data simultaneously upon a global trigger generated by a Central Logic Unit, which processes local triggers from individual channels. External and software triggers can also be configured as sources for the global trigger. Zero suppression algorithms can be applied to remove non-significant data and reduce the readout payload.
Streaming Readout Mode: Each channel autonomously identifies its ROI using the self-trigger mechanism, acquiring data independently of the other channels. This mode includes automatic zero suppression (non-triggered channels are not acquired), maximizes acquisition rates, and is ideal for applications requiring real-time parameter extraction. In addition, correlation logics can be configured to validate event acquisition upon coincidences or anticoincidences between local and external triggers.

The DT2740 can operate using both pre-configured firmware developed by CAEN and custom user-generated firmware, offering flexibility for a wide range of applications. Multiple firmware images can be stored simultaneously in the digitizer’s FLASH memory and quickly activated when needed. CAEN provides ready-to-use firmware solutions optimized for specific acquisition and processing needs:

Scope Firmware: Based on full waveform recording in triggered acquisition mode. A zero suppression function is available to reduce unnecessary data readout.
DPP-PHA Firmware: Implements Digital Pulse Processing for the pulse shape analysis. Physical parameters such as pulse height, charge and timestamp are extracted from waveforms acquired in streaming readout It is yet possible to save both raw waves and parameters.
DPP-PSD Firmware: Implements Digital Pulse Processing algorithms for charge integration and pulse shape discrimination. Physical parameters such as pulse height, charge, timestamp, and PSD are extracted from waveforms acquired in streaming readout It is yet possible to save both raw waves and parameters.
DPP-ZLEplus Firmware: Implements Digital Pulse Processing algorithms for the Zero Lenght Encoding. Data reduction is so achieveded on the recorded waveforms while they are acquired in triggered mode.

For users requiring custom acquisition and processing, the Open FPGA architecture enables firmware customization through SCI-Compiler. This graphical tool allows users to create personalized firmware solutions without HDL skills. In addition, Sci-Compiler automatically generates drivers and libraries and provides graphical utilities for developing custom DAQ software.

The Linux-based Arm processor embedded in the onboard CPU makes it possible to run automated user routines. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options. Multiple communication interfaces offer flexible readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet.

For detailed information on available firmware for the 2740 family and the structure of programming files (.CUP), please refer to the following page.

This product is compatible with the following third-party software:

PKUCAENDAQ

Ordering Options

Code	Description
WDT2740BXAAA	DT2740B – 64 Ch. 16 bit 125 MS/s Digitizer, SE	RoHS
WDT2740XAAAA	DT2740 – 64 Ch 16 bit 125MS/s Digitizer, Diff	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES

GENERAL

Weight: 3120 g (Desktop); 3170 g (Desktop Rack)
Form Factor: Desktop | Desktop Rack
Dimension: 338 W x 100 H x 283 L mm³ (Desktop without connectors) | 338 W x 100 H x 295 L mm³ (Desktop including connectors) | 19” rack mount (Desktop Rack)

ANALOG INPUT

Number of Inputs: 64, single-ended or differential, DC coupled
Bandwidth (-3dB): 50 MHz
Impedance: 50 Ω (default) or 10 kΩ (personalization by ordering code) on single-ended inputs; 100 Ω on differential inputs
ICMR (Input Common-Mode Range): ± 8 Vdc referred to GND (Differential mode only)
Gain: fixed x1
Connector Type: 2mm 40-pin header male (input adapters available)
Full Scale Range: 2 Vpp
DC Offset: Adjustable in the ± 1.25V range independently on each input channel

DIGITAL CONVERSION

Resolution: 16 bits
Sampling Rate: 125 MS/s simultaneously on each channel; scalable by 2ⁿ decimation factor (n = 1 to 10, Scope firmware only)

PERFORMANCE

ENOB (Typ.): 11.7
RMS (Typ.): 3.9 LSB (≃ 120 µV) RMS

DIGITAL I/O

LVDS I/O	TRG-IN/TRG-OUT/GPIO/S-IN
16 differential pairs Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.) LVDS Zdiff = 100 Ω (when set as inputs) 2.54mm 34-pin AMPMODU Mod II male connector	General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, veto, busy, etc.) TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω) TRG-OUT requires Rt = 50 Ω GPIO as Input must be terminated with 50 Ω GPIO as TTL Output requires Rt = 50 Ω GPIO as NIM Output requires Rt = 50 Ω or 25 Ω

ANALOG OUT

Software programmable DAC output for signal inspection, pulse generation, majority level
14-bit Digital-to-Analog Converter (DAC)
125 MS/s Update Rate
LEMO 00 connector
±1 V @ 50Ω load
±2 V @ hi-Z load Output Range

ACQUISITION MEMORY

2.5 GB total DDR4 memory size (20.971 MS/ch) divisible in multiple buffers
Maximum record length: ~84 ms @ 500 MS/s (total memory size divided by 2)¹

⁽¹⁾ Value referred to the Scope firmware (minimum of two buffers admitted)

TRIGGER AND EVENT ACQUISITION

Triggered Mode

Trigger Sources

Trigger Timestamp – Scope firmware

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals; a zero suppression function is available.

Software by register writing
External upon the leading edge of The TRG-IN signal (TTL/NIM)
Local (self-trigger) upon the channel discriminator with programmable threshold

Resolution: 8 ns coarse time stamp
Counter range: 48 bits
Full-scale range: ~625 h

Streaming Readout Mode

Each channel autonomously identifies the ROI and uses the local trigger to get events independently on the other channels; validation logics can be configured for correlated acquisition (coincidence/anticoincidence).

Trigger Timestamp – DPP firmware

Resolution: 8 ns coarse timestamp, 8 ps fine timestamp
Counter range: 48 bits
Full-scale range: ~625 h

SYNCHRONIZATION

Clock Generation

CLK-IN/CLK-OUT Connector

By default, the Digitizer’s main clocks can be optionally generated upon the internal 50MHz or external 62.5MHz reference (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

Two differential pairs:

– CLK, reference clock signal

– SYNC, synchronization signal (start/stop, T0, etc.)
2.54mm 4-pin AMPMODU Mod II male connector
CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
CLK-OUT: LVDS

Clock Synchronization

Default 62.5MHz frequency distributed by:

Fan-out to CLK-IN
CLK-IN/CLK-OUT Daisy chain with sw programmable CLK-OUT delay shift

Custom frequencies can be supported upon request.

Data Synchronization

Programmable Busy/Veto logic on differential LVDS I/O, or single-ended NIM/TTL I/O for event building.

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-out propagation through differential CLK-IN/CLK-OUT or LVDS I/O, or single-ended NIM/TTL I/O.

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/O (global trigger) or LVDS I/O (global or local trigger).

CAEN FIRMWARE

DPP Firmware (Shareware)

Scope Firmware (Freeware)

Upgrades (Free)

Pay firmware implementing a digital pulse processing algorithm:

DPP-PSD: Charge Integration, Pulse Shape Discrimination, CFD for fine timestamp
DPP-PHA: Pulse Height Analysis
DPP-ZLEplus: Zero Length Encoding

30-minute per power cycle in Trial mode; license is required for full-time work.

Designed for waveform recording.

Web available CUP files for Scope and DPP firmware upgrade via Web Interface or CAEN Toolbox software.

FPGA

Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
Programmable logic with more than 1100K system logic cells and 80Mbit memory

USER FIRMWARE (OPEN FPGA)

SCI-Compiler
User Firmware Generator and Compiler Graphical Tool for CAEN Programmable Boards.

Scope Personalization

DPP Personalization

Customizable features of the Scope firmware:

Common trigger
Simultaneous waveform recording on 64 channels management
Trigger logic
Wave processing

Customizable features of the DPP firmware:

Individual trigger and channel acquisition management
DPP algorithm
Trigger logic
Event data information

COMMUNICATION INTERFACE

1 GbE	10 GbE ⁽^Contact^{CAEN Support)}	USB 3.0
Copper RJ45 or optical LC connector on SFP+ transceiver TCP protocol Transfer rate: 110 MB/s	Copper RJ45 or LC optical connector on SFP+ transceiver UDP protocol Transfer rate: 850 MB/s	USB-C type connector USB 3.1 GEN1 protocol Transfer rate: 280 MB/s

SOFTWARE

Readout SW for CAEN Firmware (Freeware)

SCI-Compiler for Open FPGA (Shareware)

CoMPASS spectroscopy software (DPP firmware only)
WaveDump2 (Scope firmware only)

Automatic generation of drivers (USB, Ethernet), libraries, and demo software for Windows®, Linux®.

SDK and Tools (Freeware)

General-purpose libraries (C/Python) with demo samples for host Windows® and Linux® PC, and embedded Arm.

Web Interface

Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER REQUIREMENTS

Mains-powered (130 Watt @110V/220V)

DT2740

64 Input Channel 16 bit 125 MS/s Digitizer

Software

CAEN Toolbox

COMPASS

Sci-Compiler

CAEN FELib Library

WAVEDUMP2

Firmware

D-SCOPE

DPP-PSD

DPP-PHA

DPP-ZLEPLUS

DPP-SUP

Accessories

A954

A316

A319A

A319B

A372F

A372M

A952

A953

Ordering Options

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