DT5743

8 Input Channel 12bit 3.2 GS/s Switched Capacitor Digitizer

Home Modular Pulse Processing ElectronicsAnalogDigitizers DT5743

12-bit @ 3.2 GS/s ADC
Switched Capacitor technology based on the SAMLONG chip (CEA/IRFU & CNRS/IN2P3/LAL Orsay)
- 1024 capacitor cells per channel (acquisition window of ~ 320 ns @ 3.2 GS/s)
3.2 GS/s , 1.6 GS/s, 800 MS/s, 400 MS/s software selectable sampling frequencies
8 input channels, single-ended
Max. AD conversion dead-time: 125 µs @1024 samples
2.5 Vpp input range
16-bit programmable DC offset adjustment in the full range independently on each channel
Trigger Time stamps
Memory buffer (max.): 7 events/ch @1024 S/event
Pre-post trigger adjustment
Max. AD conversion dead-time: 125 µs @1024 samples
Real time hit counting independent of acquisition rate on each channel
On-board charge calculation for fast histogramming (user-defined integration window)
One embedded pulser per channel for test and reflectometry applications
Programmable PLL onboard for clock synchronization with external systems or other DT5743 units
Optical Link interface (CONET proprietary protocol) Daisy-chainable through A5818 (PCIe Gen 3) Controller or A4818 (USB3-to-CONET)
USB 2.0 communication interface
Firmware upgradeable via USB/Optical Link
Fully controlled by the WaveCatcher readout software

The CAEN Mod. DT5743 is a Waveform Digitizer, in Desktop form factor, housing 8 Channel 12 bit 3.2 GS/s ADC stage based on Switched Capacitor Digitizer arrays. This technology makes it suited for typical applications like precise characterization of high speed detectors (PMTs, SiPMs, APDs,…) and High Resolution Photon timing with MCP-PMTs.

The Switched Capacitor Array is SAMLONG chip (designed by LAL Orsay & CEA/IRFU in collaboration with CNRS/IN2P3), implementing a series of 1024 capacitors (analog memory) in which the analog input signal is continuously sampled in a circular way. The default sampling frequency is 3.2 GHz, while 1.6 GHz, 800 MHz, and 400 MHz can be software selected.

The input signal is continuously sampled at high frequency in the SAMLONG array of capacitive cells (holding phase) until the trigger arrival. The trigger stops the sampling, the analog memory buffer is frozen, and the cell content is sent to the 12-bit ADC to be digitized at lower frequency. The non-simultaneity between the Sample & Hold phase and the digital conversion generates a dead-time (up to 125 μs @1024 samples).

The acquisition takes place upon different global trigger sources, which can be the external TRG-IN, software , or the logic combination of local channel under-/over-thresholds generated from individual discriminator with programmable threshold.

The DT5743 features an embedded Charge Mode, where the pulse integration window is defined by the user (high rates ~3.5 kEvents/s). This feature allows to perform on-line processing on detector signal directly digitized.

The events are stored into the channel digital memory (up to 7 events/ch @1024 samples) to be read out through the USB or Optical Link interfaces. Multiple boards can be synchronized to build up complex systems.

This Digitizer is fully supported by WaveCatcher software, while libraries and demo software in C, Phyton, and LabView are available for integration and customization of specific acquisition systems.

Ordering Options

Code	Description
WDT5743XAAAA	DT5743 – 8 Ch. 12 bit 3.2GS/s Switched-Capacitor Digitizer: 7 events/ch (1kS/event), EP3C16, SE	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO

GENERAL

Weight: 680 g
Form Factor: Desktop
Dimension: 166 x 69 x 171 mm³ (WxHxD)

ANALOG INPUT

Number of Inputs: 8, single-ended, DC coupled
Bandwidth (-3dB): 500 MHz
Impedance: 50 Ω
Connector Type: MCX
Full Scale Range: 2.5 Vpp
16-bit programmable DC offset adjustment in the full range independently on each channel
Abs. Max. Voltage Rating: 3.5 Vpp (with Vrail max +3.5V or ‐3.5V) for any DAC offset in single ended configuration

DIGITAL CONVERSION

Resolution: 12 bits
Sampling Rate:
- 3.2 GS/s default
- 1.6 GS/s, 0.8 GS/s, 0.4 GS/s software selectable

Switched Capacitor Array: SAMLONG chip, 8 channels with 1024 storage cells each
Dead-time: max. 125 μs @1204 samples (decreasing with programmable lower record lengths)

TEST FUNCTION

One pulse generator per channel
16-bit programmable pulse pattern
Fixed amplitude: ~0.7 V with floating input
Pattern period: 3.5 µs

SYSTEM PERFORMANCES

Sampling Time Precision

Noise Level

< 20 ps @ 3.2 GS/s (before calibration)
< 5 ps @ 3.2 GS/s (after calibration)

Note: obtained with factory calibration and dual-pulse timing measurement with pulse generator.

Test conditions

Periodic input pulses with 1-V Amplitude
1-kHz Frequency Rise time of 0.8 / 1.6 / 2.5 ns.

The resolution does not change significantly when varying the delay Δt between the two pulses.

0.75 mV RMS

DIGITAL I/O

TRG-IN/GPO/GPI
General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, sync, busy, start, etc.) TRG-IN/GPI: internally terminated with 50 Ω (Zin = 50 Ω) GPO requires Rt = 50 Ω

ACQUISITION MEMORY

7 full event/ch Multi‐event buffer (1024 S/event, that is 320 ns/event @ 3.2 GS/s)
Independent read and write access
Programmable event size and pre/post‐trigger

COMMUNICATION INTERFACE

USB	Optical Link
USB 2.0 compliant Transfer Rate: up to 30 MB/s	CAEN proprietary CONET protocol Transfer Rate: up to 80 MB/s Daisy Capability: up to 8 ADC modules per single optical link by A5818 Controller or A4818 Adapter

TRIGGER AND EVENT ACQUISITION

Triggered Mode	Trigger Sources	Trigger Timestamp – Waveform Rec. firmware
All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals.	Software by register writing External upon the leading edge of The TRG-IN signal (TTL/NIM) Local (self-trigger) upon the channel discriminator with programmable threshold	Resolution: 5 ns Counter range:40 bits Full-scale range: ~ 83 min

SYNCHRONIZATION

Clock Generation

CLK-IN Connector

By default, the Digitizer’s main clocks are generated upon a 50MHz reference frequency that can optionally be internal (50MHz local Oscillator) or external (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

Reference clock differential signal
2.54mm 3-pin AMPMODU Mod II male connector
AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)

Clock Synchronization

Default 50MHz frequency distributed by:

Fan-in into CLK-IN (DT4700)

PLL programming files for supported custom frequencies can be generated and loaded by the CAEN Toolbox software.

Data Synchronization

Programmable Busy/Veto logic on single-ended NIM/TTL I/O for event building (external hardware required).

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-in propagation through single-ended TRG-IN/GPO/GPI connectors (NIM/TTL).

Trigger Distribution

Optionally, by Daisy chain or fan-out propagation through single-ended TRG-IN/GPO connectors, NIM/TTL (global trigger).

FPGA

Altera Cyclone EP3C16
1 FPGA serves 4 channels

CAEN FIRMWARE

Waveform Recording Firmware (Freeware)	Upgrades (Free)
Default mode: waveform recording Charge mode: charge integration, software selectable	Web available CFA files for Waveform Recording firmware upgrade through the CAEN Toolbox software, via VMEbus or Optical Link.

SOFTWARE

Readout Software for Waveform Rec. Firmware (Freeware)	SDK and Tools (Freeware)
CAEN WaveCatcher: GUI-based application for the 743 Digitizer series, developed in LabWindows/CVI by CNRS/IN2P3/LAL, and capable to fully control single-board and multi-board syncronized systems.	General-purpose libraries (C/Python, LabVIEW) with demo samples for host Windows® and Linux® PC.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER CONSUMPTIONS

1.5 A @ +12 V DC (Typ.)
AC‐DC 12 V / 45 W power unit included

DT5743

8 Input Channel 12bit 3.2 GS/s Switched Capacitor Digitizer

Software

CAEN Toolbox

CAENDigitizer Library

WAVECATCHER

WaveDemo x743

Firmware

D-WAVE

Accessories

A318

DT4700

A317

A319B

AI2700

A654

A659

Ordering Options

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