N6730 / N6730S

8 Channel 14-bit 500 MS/s Digitizer

Home Modular Pulse Processing ElectronicsAnalogDigitizers N6730 / N6730S

14-bit @ 500 MS/s
Analog inputs on MCX coaxial connectors
NSCLDAQ Supported (DPP-PSD and DPP-PHA only)
8 channels, 1-unit wide NIM module
0.5 and 2 Vpp selectable input dynamic range with programmable DC offset adjustment
Algorithms for Digital Pulse Processing (Free Trial)
- Pulse Height Analysis (DPP-PHA)
- Pulse Shape Discrimination (DPP-PSD)
- Zero Length Encoding (DPP-ZLEplus) –NEW
- Dynamic Acquisition Window (DPP-DAW) –NEW
USB and Optical Link communication interfaces
Multi-board synchronization features
Daisy chain capability
Compliant with CoMPASS, MC²Analyzer, DPP-ZLEplus and DPP-DAW Demo Software, C and LabVIEW libraries

The N6730S is a digitizer capable of recording waveforms along with performing advanced algorithms for online digital pulse processing (DPP) (Free Trial). Utilizing DPP Firmware, users can acquire quantitative physical parameters (Integrated Charge, Pulse Shape Discrimination with very fine time resolution, Pulse Height Analysis) as well as read out waveforms with automatic pulse identification and baseline suppression on channel basis (Zero-Length Encoding and Dynamic Acquisition Window). The wide range of DPP algorithms supported by the N6730S make it a “must-have” for any type of nuclear physics application.

The N6730S (previously N6730) has also been upgraded, introducing a larger FPGA to accommodate more complex DPP algorithms and a new A/D converter for better stability which does not require temperature-related calibration.

Input signals are read by a Flash ADC, 14-bit resolution and 500 MS/s sampling rate, which is well suited for mid fast signals as the ones coming from liquid or inorganic scintillators coupled to PMTs or Silicon Photomultipliers, but also for high precision detectors as Silicon or HPGe coupled with charged sensitive preamplifier. The acquisition can be channel independent and it is possible to make coincidence/anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems. In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improving the throughput performances. Piled-up events can be rejected or saved for offline analysis. The acquisition in DPP mode is fully controlled by the CoMPASS and MC²Analyzer software, which manage the algorithm parameters, build the plots and saves the relevant energy, time, and PSD spectra. In the case of waveform recording mode, the user can take advantage of the CAENScopeand WaveDump software to access and save the waveforms. Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The N6730S comes in a NIM form factor, with 8 input channels. The communication to and from the board is provided through the USB and Optical Link interfaces.

Ordering Options

Code	Description
WN6730BXAAAA	N6730B – 8 Ch. 14 bit 500 MS/s Digitizer: 5.12MS/ch, CE30, SE (Obsolete)	RoHS
WN6730SBXAAA	N6730SB – 8 Ch. 14 bit 500 MS/s Digitizer: 5.12MS/ch, Arria V GX, SE	RoHS
WN6730SXAAAA	N6730S – 8 Ch. 14 bit 500 MS/s Digitizer: 640kS/ch, Arria V GX, SE	RoHS
WN6730XAAAAA	N6730 – 8 Ch. 14 bit 500 MS/s Digitizer: 640kS/ch, CE30, SE (Obsolete)	RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO


GENERAL	Form Factor: 1-unit wide NIM
ANALOG INPUT	Channels: 8 channels single ended Impedance: 50 Ω Connector: MCX Full Scale Range: 0.5 or 2 Vpp (SW selectable) Bandwidth: 250 MHz Offset: Programmable DAC for DC offset adjustment in the full scale range
DIGITAL CONVERSION	Resolution: 14 bits Sampling Rate: 500 MS/s Simultaneously on each channel
SYSTEM PERFORMANCES	N6730Sx Baseline RMS Noise (open inputs) @ 2 Vpp: 2.6 LSB = 312 uV @ 0.5 Vpp: 3.4 LSB = 102 uV
ADC Clock Generation	Clock source: internal/external Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference
DIGITAL I/O	CLK-IN (AMP Modu II) AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter) Jitter <100 ppm requested GPO (LEMO) General purpose digital output NIM/TTL, Rt = 50 Ω GPI (LEMO) General purpose digital input NIM/TTL, Zin = 50 Ω TRG-IN (LEMO) External trigger digital input NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY	640 kS/ch (1.25 ms @ 500 MS/s) or 5.12 MS/ch (10 ms @ 500 MS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers Independent read and write access Programmable event size and pre/post-trigger
TRIGGER	Trigger Source Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation External-trigger: Common by TRG-IN connector Software-trigger: Common by software command Trigger Propagation GPO digital output Trigger Time Stamp Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware DPP-PSD: 47-bit counter, 2 ns resolution, 78 h range; 10-bit and 2 ps fine time stamp with digital CFD DPP-PHA: 47-bit counter, 2 ns resolution, 78 h range DPP-DAW: 48-bit counter, 2 ns resolution, 156 h range DPP-ZLEplus: 48-bit counter, 16 ns resolution, 625 h range
SYNCHRONIZATION	Clock Propagation One-to-many: clock distribution from DT4700 to CLK-IN connector Acquisition Synchronization Sync Start/Stop through digital I/O (TRG-IN input, GPO output) Trigger Time Stamp Alignment By GPI input connector
ADC & Memory Controller FPGA	N6730 Altera Cyclone EP4CE30 (one FPGA serves 4 channels) N6730S Intel/Altera Arria V GX (one FPGA serves 4 channels)
COMMUNICATION INTERFACES	USB USB 2.0 compliant Transfer rate up to 30 MB/s Optical Link CAEN CONET proprietary protocol, up to 80 MB/s transfer rate Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod.A2818/A3818)
FIRMWARE	Waveform Recording Firmware Free firmware for waveform recording Upgrades Firmware can be upgraded via Optical Link or USB DPP Firmware Paid firmware for Digital Pulse Processing: DPP-PSD, DPP-PHA, DPP-ZLEplus, and DPP-DAW
POWER CONSUMPTIONS	4.9 A @ +6V 250 mA @ -6V

N6730 / N6730S

8 Channel 14-bit 500 MS/s Digitizer

Software

CAEN Toolbox

CAENDigitizer Library

COMPASS

MC²Analyzer

WAVEDUMP2

Accessories

A4818

A318

A317

A5818

AI2700

A654

A659

Ordering Options

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