DT5724

4/2 Input Channel 14 bit 100 MS/s Digitizer

Home Modular Pulse Processing ElectronicsAnalogDigitizers DT5724

14 bit 100 MS/s ADC
FPGA for real time Digital Pulse Processing::
4/2 input channels (single-ended)
2.25 Vpp input range (default); 10 Vpp and 0.5 Vpp customization by ordering option
16-bit programmable DC offset adjustment in the full range independently on each channel
Sampling rate decimation factor
Trigger Time stamps
Multi-Event Memory buffer: 512 kS/ch or 4 MS/ch, divisible into up to 1024 buffers
Programmable event size and pre-post trigger adjustment
Programmable PLL onboard for clock synchronization with external systems or other DT5724 units
Optical Link interface (CONET proprietary protocol) Daisy-chainable through A5818 (PCIe Gen 3) Controller or A4818 (USB3-to-CONET)
USB 2-0 communication interface
Firmware upgradeable via USB/Optical Link
Fully supported by CoMPASS and WaveDump2 software

The CAEN Mod. DT5724 is a Waveform Digitizer, in the Desktop form factor, housing 4/2 Input Channel 14-bit 100 MS/s Flash ADC, designed for waveform recording and supporting advanced algorithms for online digital pulse processing (DPP).

The individual DC offset adjustment by programmable 16bit DACs allows the effective sampling of either bipolar, or full positive, or negative analog input swing without losing dynamic resolution.

The module features front panel Clock Input and mounts a PLL for the clock synthesis upon internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either by USB or Optical Link. The acquisition can continue without dead time in a new buffer.

The model is available in 4 versions: with 2 or 4 channels, different Multi Event Buffer memory and different FPGA densities:

Version	DT5724B	DT5724F	DT5724C	DT5724G
No of Channels	4	4	2	2
Cyclone FPGA	EP1C20 (20.000 LEs)	EP1C20 (20.000 LEs)	EP1C20 (20.000 LEs)	EP1C20 (20.000 LEs)
Memory	512kS/ch	4MS/ch	512kS/ch	4MS/ch

Each channel has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of programmable size. “Zero suppression” and “data reduction” algorithms allow substantial savings in data amount readout and processing, rejecting samples smaller than a programmable threshold. The DT5724 supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger Time Stamp and and Data alignment.

The trigger for the event acquisition can be provided either externally via the front panel Trigger Input, or by software command, or it is internally generated upon the self-trigger capability (i.e. individual discriminator on each channel with programmable threshold).

The DT5724 houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The Optical Link, based on the CAEN proprietary CONET protocol, supports transfer rate up tp 80 MB/s as well as Daisy chain capability. Therefore, it is possible to connect up to 8 ADC modules to the single-link A4818 Adapter, while up to 32 ADC modules to the 4-link A5818 .

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C, Python, and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

CAEN Toolbox: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
CAEN WaveDump: C-based readout program for the single-board management or Digitizer 1.0 Series running the Waveform Recording firmware, provided with source files for user customization.
WaveDump2: Open source GUI-based application for the single and multi-board management of Digitizer 2.0 and 1.0 Series running the Waveform Recording / Scope firmware.
CoMPASS: Multiparametric DAQ Software for Physics Applications with single and multi-board support of Digitizer 2.0 and 1.0 Series running the DPP firmware.

CAEN provides also for this model Digital Pulse Processing firmware for Physics Applications. This feature allows to perform on-line processing on detector signal directly digitized:

Ordering Options

Code	Description
WDT5724AXAAA	DT5724A – 2 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE (Obsolete)
WDT5724BXAAA	DT5724B – 4 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C20, SE	RoHS
WDT5724CXAAA	DT5724C – 2 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C20, SE	RoHS
WDT5724DXAAA	DT5724D – 4 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE (Obsolete)
WDT5724EXAAA	DT5724E – 2 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE (Obsolete)
WDT5724FXAAA	DT5724F – 4 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE	RoHS
WDT5724GXAAA	DT5724G – 2 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE	RoHS
WDT5724XAAAA	DT5724 – 4 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE (Obsolete)

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO

GENERAL

Weight: 680 g
Form Factor: Desktop
Dimension: 154x50x164 mm³ (WxHxD)

ANALOG INPUT

Number of Inputs: 4/2, single-ended, DC coupled
Bandwidth (-3dB): 40 MHz
Impedance: 50 Ω
Gain: x1, fixed
Connector Type: MCX
Full Scale Range: 2.25 Vpp deafult; 10 Vpp and 0.5 Vpp customization by ordering option
16-bit programmable DC offset adjustment in the full range independently on each channel
Abs. Max. Voltage Rating: 6 Vpp @2.25Vpp (with Vrail max +6 V or –6 V for any DAC offset value)

DIGITAL CONVERSION

Resolution: 14 bits
Sampling Rate:
- 100 MS/s simultaneously on each channel (nominal)
- Down to 16.1 MS/s by hardware downsampling* (AN6308)
- Down to 781 kS/s by firmware decimation (Waveform Recording firmware only)

*The minimum value may depend on the digitizer model, the firmware, and the hardware downsampling mode.

SYSTEM PERFORMANCES

ENOB: 11.89 (64 kS Buffer)
SINAD: 73.85 dB
THD: 87.8 dB
SFDR: 93.5 dB
SIGMA: 1.09 LSB rms (64 kS buffer, open input)

DIGITAL I/O

TRG-IN/GPO/GPI
General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, veto, busy, etc.) TRG-IN/GPI: Zin = 50 Ω (internally terminated) GPO requires Rt = 50 Ω

ACQUISITION MEMORY

512 kS/ch (5 ms @ 100 MS/s) or 4 MS/ch (40 ms @ 100 MS/s) Multi Event Buffer divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre/post-trigger

COMMUNICATION INTERFACE

USB	Optical Link
USB 2.0 compliant Transfer Rate: up to 30 MB/s	CAEN proprietary CONET protocol Transfer Rate: up to 80 MB/s Daisy Capability: up to 8 ADC modules per single optical link by A5818 Controller or A4818 Adapter

TRIGGER AND EVENT ACQUISITION

Triggered Mode

Trigger Sources

Trigger Timestamp – Waveform Rec. firmware

All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals; a zero suppression function is available.

Software by register writing
External upon the leading edge of The TRG-IN signal (TTL/NIM)
Local (self-trigger) upon the channel discriminator with programmable threshold

Resolution: 20 ns
Counter range: 31 bits (default); extendable to 48-bit by firmware
Full-scale range: ~ 21 s @31-bit

Streaming Readout Mode

Trigger Timestamp – DPP firmware

Each channel autonomously identifies the ROI and uses the local trigger to get events independently on the other channels; validation logics can be configured for correlated acquisition (coincidence/anticoincidence).

DPP-PHA:

Resolution: 10 ns
Counter Range: 30 bits (default); extendable to 46-bit by firmware, to 64-bit by software
Full-scale range: ~ 10 s @30-bit

DPP-DAW:

Resolution: 10 ns
Counter Range: 31-bit (default); extendable to 64-bit by software
Full-scale range: ~ 21 s @31-bit

SYNCHRONIZATION

Clock Generation	CLK-IN Connector
By default, the Digitizer’s main clocks are generated upon a 50MHz reference frequency that can optionally be internal (50MHz local Oscillator) or external (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.	Reference clock differential signal 2.54mm 3-pin AMPMODU Mod II male connector AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
Clock Synchronization	Data Synchronization
Default 50MHz frequency distributed by: Fan-in into CLK-IN (DT4700) PLL programming files for supported custom frequencies can be generated and loaded by the CAEN Toolbox software.	Programmable Busy/Veto logic on single-ended NIM/TTL I/O for event building (external hardware required).
Run Synchronization (Acqusition Start/Stop) Optionally, by Daisy chain or fan-in propagation through single-ended TRG-IN/GPO/GPI connectors (NIM/TTL)	Trigger Distribution Optionally, by Daisy chain or fan-out propagation through single-ended TRG-IN/GPO connectors, NIM/TTL (global trigger)

FPGA

Altera Cyclone EP1C20
One FPGA serves 1 channel

CAEN FIRMWARE

DPP Firmware (Shareware)

Waveform Recording Firmware (Freeware)

Upgrades (Free)

Pay firmware implementing a digital pulse processing algorithm:

DPP-PHA: Pulse Height Analysis
DPP-DAW: Dynamic Acquisition Window

30-minute per power cycle in Trial mode; license is required for full-time work.

Designed for waveform recording.

Web available CFA files for Waveform Recording and DPP firmware upgrade through the CAEN Toolbox software, via USB or Optical Link.

SOFTWARE

Readout Software for Waveform Rec. Firmware (Freeware)	Readout Software for DPP Firmware (Freeware)	SDK and Tools (Freeware)
CAEN WaveDump: Digitizer 1.0 series support, single-board management, user-customizable WaveDump2: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based	CoMPASS: support for DPP-PHA of Digitizer 1.0 and 2.0 series, single and multi-board management, GUI based DPP-DAW Readout Demo: sample code with C source files to dial with the DAW functionalities and help in user’s DAQ development	General-purpose libraries (C/Python, LabVIEW) with demo samples for host Windows® and Linux® PC.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER CONSUMPTIONS

1.7 A @ +12 V DC (Typ.)
AC‐DC 12 V / 45 W power unit included

DT5724

4/2 Input Channel 14 bit 100 MS/s Digitizer

Software

CAEN Toolbox

CAENDigitizer Library

COMPASS

WaveDump

CAEN FELib Library

WAVEDUMP2

Firmware

D-WAVE

DPP-PHA

DPP-DAW

DPP-SUP

Accessories

A4818

Digitizers Input Range Personalizations

A318

DT4700

A317

A319B

AI2700

A654

A659

Ordering Options

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