VX1740

64 Input Channel 12bit 62.5 MS/s Digitizer

Home Modular Pulse Processing ElectronicsAnalogDigitizers VX1740

12 bit 62.5 MS/s ADC
64 input channels (single-ended)
High density input connectors, ERNI SMC Dual Row 68-pin (32 pairs)
2 Vpp input range (default); 10-Vpp version by ordering option
16-bit programmable DC offset adjustment in the full range independently on each channel
Sampling rate decimation factor
Trigger Time stamps
Multi-Event Memory buffer: 192 kS/ch or 1.5 MS/ch, divisible into up to 1024 buffers
Programmable event size and pre-post trigger adjustment
Analog Sum/Majority and digital over/under threshold flags for Global Trigger logic
Front panel clock input/output available for multiboard synchronization (direct feed through or PLL-based synthesis)
16 programmable LVDS I/Os
Optical Link interface (CONET proprietary protocol) Daisy-chainable through A5818 (PCIe Gen 3) Controller or A4818 (USB3-to-CONET)
VME64X interface
Firmware upgradeable via VME/Optical Link
Fully supported by WaveDump and WaveDump2 software

The CAEN Mod. VX1740 is a Waveform Digitizer, in VME64X form factor, housing 64 Input Channel 12 bit 62.5 MS/s Flash ADC, designed for waveform recording. The Digitizer is well suited for mid-slow signals generally coming from inorganic scintillators coupled with PMTs, gaseous detectors, and others.

The module features front panel Clock Input/Output and a PLL for clock synthesis and distribution from internal/external references. The event acquisition takes place upon the trigger arrival, in triggered mode for the waveform recording firmware (global trigger). Basically, the trigger source can be either external via the front panel connectors (differential and single-ended), or by software command, or it can be locally generated thanks to self-trigger capability.

Due to the high input density, In the trigger domain, the inputs of the VX1740 are managed as 8‐channel groups. The acquisition digital memory is a SRAM Multi-Event Buffer of 192 kS/ch or 1.5 MS/ch divisible into 1 ÷ 1024 buffers of programmable size.

The VX1740 is optimized for multi-board system building, allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple VX1740 boards.

The full communication with the VX1740 is possible either via the VMEbus or Optical Link interface. The VME interface allows for transfer rates up to 60 MB/s by using CAEN Bridges (V3718/V4718). The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability; therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A4818/A5818).

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

CAEN Toolbox: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.

Waveform Recording Firmware compliant:

CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.
WaveDump2: Open source GUI-based application for the single and multi-board management of Digitizer 2.0 and 1.0 Series running the Waveform Recording / Scope firmware.

Note: VX1740 can be operated with VME8004X / VME8008X /VME8100 / VME8200 /μ-crate.

Ordering Options

Code	Description
WVX1740AXAAA	VX1740A – 10Vpp 64 Ch. 12 bit 62.5 MS/s Digitizer: 1.5 MS/ch, EP3C16, SE	RoHS
WVX1740BXAAA	VX1740B – 64 Ch. 12 bit 62.5 MS/s Digitizer: 1.5 MS/ch, EP3C16, SE	RoHS
WVX1740CXAAA	VX1740C – 10Vpp 64 Ch. 12 bit 62.5 MS/s Digitizer: 192 KS/ch, EP3C16, SE	RoHS
WVX1740XAAAA	VX1740 – 64 Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE	RoHS

Add to Wishlist

Request a Quote

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	V1740	VME	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO

GENERAL

Weight: 535 g
Form Factor: 1-unit wide VME64X
Dimension: 6U x 160 mm

ANALOG INPUT

Number of Inputs: 64, single-ended, DC coupled
Bandwidth (-3dB): 30 MHz
Impedance: 50 Ω (2-Vpp model), 1 kΩ (10-Vpp model)
Connector Type: 64-pin Dual Row ERNI SMC
Full Scale Range: 2 Vpp default; 10 Vpp by ordering option
16-bit programmable DC offset adjustment in the full range independently on each channel
Abs. Max. Voltage Rating: 6 Vpp @2Vpp (with Vrail max +6 V or –6 V) for any DAC offset value

DIGITAL CONVERSION

Resolution: 12 bits
Sampling Rate:
- 62.5 MS/s simultaneously on each channel (nominal)
- Down to 488 kS/s by decimation function (Waveform Recording firmware only)

SYSTEM PERFORMANCE

ENOB: 11.20 (48 kS Buffer)
SINAD: 69.20 dB (48 kS Buffer, open input)
THD: 87.10 dB
SFDR: 94.9 dB
SIGMA: 0.50 LSB rms

DIGITAL I/O

LVDS I/O	TRG-IN/TRG-OUT/S-IN
16 differential pairs Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.) LVDS Zdiff = 100 Ω (when set as inputs) 2.54mm 34-pin AMPMODU Mod II male connector	General-purpose digital I/Os Sigle-ended TTL/NIM LEMO 00 male connector Software programmable function (trigger, veto, busy, etc.) TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω) TRG-OUT requires Rt = 50 Ω

ANALOG OUT

Software programmable DAC output (12-bit/125MHz) with four operating modes:
- Test Waveform: 1 Vpp test ramp generator
- Majority signal: proportional to the number of channels (enabled) under/over threshold (1 step = 125 mV)
- Buffer Occupancy: output signal is proportional to the Multi Event Buffer Occupancy (1 buffer ~ 1 mV)
- Voltage level: output signal is a programmable voltage level (0 to +1 V range with 12-bit resolution)

ACQUISITION MEMORY

192k sample/ch (3 ms @ 62.5 MS/s) or 1.5M sample/ch (24 ms @ 62.5 MS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre/post-trigger

COMMUNICATION INTERFACE

VMEbus	Optical Link
VME64X Data modes: D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast Cycles Transfer Rate: 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST) Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access	CAEN proprietary CONET protocol Transfer Rate: up to 80 MB/s Daisy Capability: up to 8 ADC modules per single optical link by A5818 Controller or A4818 Adapter

TRIGGER AND EVENT ACQUISITION

Triggered Mode	Trigger Sources	Trigger Timestamp – Waveform Rec. firmware
All the channels fire simultaneously upon a global trigger generated by the Central Logic Unit receiving the trigger source signals. In the trigger domain, the inputs of the VX1740 are managed as 8‐channel groups.	Software by register writing External upon the leading edge of The TRG-IN signal (TTL/NIM) Local (self-trigger) upon the channel discriminator with programmable threshold	Resolution: 16 ns Counter range: 31 bits (default); extendable to 48-bit by firmware Full-scale range: ~ 17 s @31-bit

SYNCHRONIZATION

Clock Generation

CLK-IN/CLK-OUT Connector

By default, the Digitizer’s main clocks are generated upon a 50MHz reference frequency that can optionally be internal (50MHz local Oscillator) or external (CLK-IN). Onboard programmable PLL allows locking to different external frequencies.

Reference clock differential signal
2.54mm 3-pin AMPMODU Mod II male connector
CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
CLK-OUT: LVDS

Clock Synchronization

Default 50MHz frequency distributed by:

Fan-in into CLK-IN (DT4700)
CLK-IN/CLK-OUT Daisy chain with sw programmable CLK-OUT delay shift

PLL programming files for supported custom frequencies can be generated and loaded by the CAEN Toolbox software.

Data Synchronization

Programmable Busy/Veto logic on differential LVDS I/O, or single-ended NIM/TTL I/O for event building.

Run Synchronization (Acquisition Start/Stop)

Optionally, by Daisy chain or fan-in propagation through differential CLK-IN/CLK-OUT or LVDS I/O, or single-ended NIM/TTL I/O.

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/O (global trigger) or LVDS I/O (global or local trigger).

ADC Sampling Clock generation

Clock source: internal/external
On-board programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

FPGA

Altera Cyclone EP1C16
One FPGA serves 16 channels

CAEN FIRMWARE

Waveform Recording Firmware (Freeware)	Upgrades (Free)
Designed for waveform recording.	Web available CFA files for Waveform Recording firmware upgrade through the CAEN Toolbox software, via VMEbus or Optical Link.

SOFTWARE

Readout Software for Waveform Rec. Firmware (Freeware)	SDK and Tools (Freeware)
CAEN WaveDump: Digitizer 1.0 series support, single-board management, user-customizable WaveDump2: Digitizer 1.0 and 2.0 series support, single and multi-board management, GUI based	General-purpose libraries (C/Python, LabVIEW) with demo samples for host Windows® and Linux® PC.

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER CONSUMPTIONS

+5 V: 5.6 A (Typ.)
+12 V: 0.25 A (Typ.)
-12V: not used

VX1740

64 Input Channel 12bit 62.5 MS/s Digitizer

Software

CAEN Toolbox

CAENDigitizer Library

WaveDump

CAEN FELib Library

WAVEDUMP2

Firmware

D-WAVE

Accessories

A954

A316

A318

A746B

DT4700

A317

A319B

A371

AI2700

A952

A953

Ordering Options

You also may be interested in…

A4818

µ-crate

DT5740

VME8100

VME8200

A5818

V1740

VME8004X

VX3718

VX4718

VME8008X

Request a Quote

Compare

Technical Specifications

Footer

About Us

Resources

Applications

Support

News

Contact Us

Login